To enable fractional-$N$frequency synthesis in a phase locked loop (PLL), the instantaneous division ratio of a multi-modulus divider is usually controlled by a digital$\Delta $-$\Sigma $modulator (DDSM). The accumulated quantization error (AQE) of the DDSM is injected into the loop. When distorted by inevitable nonlinearities within the loop, the distorted AQE gives rise to fractional spurs; these degrade the spectral purity and jitter of the synthesized signal. In this paper, we present a unified analysis of representative DDSMs in terms of their architectures and working principles. Their AQE’s variation range, variance (power), statistical distribution, spectral signature, and immunity to fractional spurs in the presence of nonlinear distortions are also characterized. In particular, we study and compare the classic family of Multi-stAge noise-SHaping (MASH) DDSMs and two state-of-the-art families: probability-density-shaping (PDS) and Enhanced Nonlinearity-induced nOise Performance (ENOP) DDSMs. Building on the prior art, we propose a novel family of Probability density And Spectral envelope Shaping (PASS) DDSMs which, while guaranteeing the maximum spur immunity for a given variation range of the AQE, also provide optimized shaping for fractional-$N$frequency synthesis in terms of both the probability distribution and spectral envelope of the AQE to avoid high frequency phase noise “bumps” and/or “plateaus”.

Digital-to-time converters (DTC’s) used in fractional-N frequency synthesizers attempt to cancel the accumulated quantization error (QE) introduced by the divider controller with a view to recovering the integer-N phase noise (PN) performance. The resolution of the DTC needs to be sufficiently fine to suppress its own QE below the intrinsic integer-N jitter and, at the same time, sufficiently coarse to limit the DTC’s hardware needs. In this manuscript, we propose optimal strategies to determine the effective dynamic range, number of bits, quantization resolution, and unity delay of the DTC to achieve these goals; the additional jitter power introduced by input-dithered quantization methods to eliminate DTC-quantization-induced spurs is also considered. DTCs parameterized following these strategies can come close to realizing the spur-free integer-N PN with minimum hardware. Behavioral simulations confirm our analysis.

Digital-to-time converters (DTC’s) used in fractional-N phase locked loops (PLL’s) aim to zero the quantization error (QE) introduced by the divider controller in order to recover integer-N phase noise (PN) performance. Unfortunately, the inherent quantization behavior and integral nonlinearity associated with the DTC mean that the aforementioned QE cannot be canceled exactly; inevitably, the residual error gives rise to additional PN and spurious tonal phenomena. This tutorial paper uses DTC macromodels to analyze and distinguish the DTC’s sources of nonideality and the distinct adverse spectral responses induced by them. Different DTC enhancement techniques are shown to mitigate certain types of nonideality. A comprehensive design strategy incorporating these techniques is proposed, which mitigates the revealed excess PN and spurs introduced by the DTC’s nonidealities. The enhanced DTC enables the fractional-N DPLL to approach the fractional-spur-free integer-N PN performance limit. Behavioral simulations at both DTC-block and PLL-system levels confirm our analysis.

The mid-rise time-to-digital converter (TDC), e.g., a binary (bang-bang) phase detector and other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked loop (DPLL) because of the design simplicity and ultra-low consumption in terms of area and power. However, its hard quantization nonlinearity makes it nontrivial to estimate its linearized gain and the power of the quantization error (QE) that it introduces, and hence can make the linearized analysis at the DPLL-system level inaccurate. This tutorial paper formulates a minimum-mean-square-error estimator that is used to provide an accurate linearized analysis of the TDC; it takes into account the interaction between the quantization characteristic of the TDC and the statistical properties of the input jitter of a frequency synthesizer in both integer-$N$and fractional-$N$modes. A strategy for minimizing the TDC’s QE is provided; so-designed TDCs with equidistant quantization thresholds are able to achieve optimum jitter minimization at both the TDC and DPLL levels. Finally, the effective linear operating region of such TDCs is derived, which explains when the “hard quantizer” can be regarded as an almost linear PD and when not. Behavioral simulations at the TDC-block and DPLL-system levels underpin our analysis.

The digital-to-time converter (DTC) used in fractional-Nphase locked loops is designed to cancel the accumulated quantization error (QE) arising from the divider controller. In high-resolution synthesizers, the DTC performs an additional quantization when mapping the required high-resolution phase correction to its coarse-resolution output. This inherent hard quantization nonlinearity of the DTC, which is different from the DTC’s well-known soft integral nonlinearity, causes yet another kind of inexact cancellation of the QE and induces excess spurious tones that degrade the output phase noise and jitter. This paper reveals the root cause of the “DTC’s QE” and spectral manifestation of the DTC-quantization-induced (DQI) spurs. The waveform of the DTC’s QE is derived analytically; it shows that the DQI-spur pattern is (i) determined by the fractional frequency control word and the quantization resolution of the DTC, and (ii) is independent of the type, order, and modulus of the divider controller. In view of the fact that conventional DTC linearity enhancement techniques and stochastic divider controllers have no effect on DQI-spur mitigation, we propose a novel family of DTC-enhancement methods called input-dithered quantization (IDQ). When used in DTCs, the IDQ methods are effective in eliminating DQI spurs at source with negligible phase noise or jitter penalty.

Digital-to-time converters (DTC’s) that are based on a controllable delay line are used in fractional-N frequency synthesizers to cancel the quantization error (QE) introduced by the divider controller in order to recover the integer-N phase noise performance. To relax the control complexity and reduce the hardware demand, the DTC delay line can be segmented into a cascade of coarse and fine components. This paper compares two state-of-the-art DTC segmentation topologies and their control methods. We will show that the convergence of the least-mean-square algorithm auto-calibrating the DTC’s gain is an important issue that affects the success of the DTC-based QE cancellation when small fractional frequency control words are used. Behavioral simulations analyzed in the time and frequency domains underpin our study.

Bang-bang digital phase locked loops (BBDPLL’s) use a binary phase detector (BPD) to limit the complexity and consumption of area and power of the time-to-digital converter (TDC), which inevitably introduces more quantization errors (QE’s) than a conventional high-resolution TDC. Coarse-resolution TDCs with a few more bits than the BPD can help to mitigate the TDC-induced output jitter and phase noise (PN). This paper derives estimates of the RMS input and output jitters of such digital phase locked loops (DPLL’s) with mid-rise TDCs, including BBDPLLs, based on a multi-rate discrete-time model. A comprehensive jitter minimization strategy is provided. The impact of this type of jitter minimization on the enhancement of the output PN performance is studied for the first time. Behavioral simulations verify our analysis. Finally, we conclude with design rules of thumb and a design procedure that helps to mitigate the system jitter and to achieve an output PN spectrum that is dominated by the noises contributed by the reference and digitally controlled oscillator (DCO).