VLDB 2026 Research / reviewers in the wild / expert
David Hoyes
dblp:182/9264
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 1Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Processor architecture and microarchitecture · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.2 | 1 | 2016 | End-to-End Verification of Processors with ISA-Formal · CAV (2) 2016 |
Processor architecture and microarchitecture
instruction set architecture |
0.2 | 1 | 2016 | End-to-End Verification of Processors with ISA-Formal · CAV (2) 2016 |
Electronic design automation › hardware verification and test
processor verification |
0.2 | 1 | 2016 | End-to-End Verification of Processors with ISA-Formal · CAV (2) 2016 |
Methods — techniques the papers use, named apart from their topics
formal verification · 0.2ISA-formal · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | End-to-End Verification of Processors with ISA-Formal
Alastair Reid 0001, Rick Chen, Anastasios Deligiannis, David Gilday, David Hoyes, Will Keen, Ashan Pathirane, Owen Shepherd, Peter Vrabel, Ali Zaidi |
CAV (2) | 5 |