VLDB 2026 Research / reviewers in the wild / expert
Ninghua Zhu
dblp:183/1458
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0002-1824-8317ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
2 papers |
Optical networks · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 68% Electronic design automation · 32% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Optical networks
microwave photonics |
1.6 | 2 | 2025 | Silicon integrated microwave photonics · Sci. China Inf. Sci. 2025 Simultaneous microwave characterization of wafer-level optoelectronic transceiver chips based on photonic sampling and mapping · Sci. China Inf. Sci. 2024 |
Integrated circuit design
photonic integrated circuits |
0.3 | 1 | 2025 | Silicon integrated microwave photonics · Sci. China Inf. Sci. 2025 |
Integrated circuit design
optoelectronic integrated circuits |
0.2 | 1 | 2024 | Simultaneous microwave characterization of wafer-level optoelectronic transceiver chips based on photonic sampling and mapping · Sci. China Inf. Sci. 2024 |
Electronic design automation › hardware verification and test › VLSI testing
wafer testing |
0.2 | 1 | 2024 | Simultaneous microwave characterization of wafer-level optoelectronic transceiver chips based on photonic sampling and mapping · Sci. China Inf. Sci. 2024 |
Methods — techniques the papers use, named apart from their topics
photonic sampling · 1.5photonic mapping · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Silicon integrated microwave photonicsabstractAbstract The generation, processing, and measurement of microwave signals using optoelectronic technology on compact chips represent a significant trend in the evolution of microwave photonics (MWP). Among various platforms, silicon photonics has emerged as a leading choice, primarily due to its compatibility with established complementary metal-oxide-semiconductor (CMOS) processes. This compatibility enables the complete integration of high-performance radio frequency (RF) links while addressing key challenges such as size, power consumption, cost, and reliability. In this article, we review recent advancements in silicon-integrated microwave photonics, focusing on the developments of device-level integration and system-level applications. At the device level, we highlight critical innovations in silicon-based passive and active components towards MWP concerns, including ultralow-loss waveguides, high-fitness micro rings, large-bandwidth/high-linearity electro-optic modulators, hybrid/heterogeneous integrated lasers and amplifiers on silicon, frequency combs, and more. These breakthroughs form the basic foundation for advancing MWP system-level implementation. At the system-level applications, we concentrate on integrated MWP systems with diverse functionalities on silicon chips, including microwave signal generation, processing, programmable circuits, and measurement systems. Finally, we discuss current challenges and provide insights into the future of silicon-integrated MWP. Yuansheng Tao, Zihan Tao, Bitao Shen, Luwen Xing, Wencan Li, Huajin Chang, Jingmei Zhang, Haowen Shu, Ninghua Zhu |
Sci. China Inf. Sci. | 12 |
| 2024 | Simultaneous microwave characterization of wafer-level optoelectronic transceiver chips based on photonic sampling and mapping
Xinhai Zou, Naidi Cui, Junbo Feng, Shang-Jian Zhang, Ninghua Zhu |
Sci. China Inf. Sci. | 11 |
| 2023 | A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/OabstractThis paper presents a 50-Gb/s optical receiver (ORX) chipset, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit in a 45-nm silicon-on-insulator CMOS. The proposed inverter-based TIA employs hybrid shunt-series peaking inductors to extend the bandwidth (BW). A baud-rate CDR is proposed to reduce the sampling phases and clocking power by half. To optimise the ORX for in- package integration, a compact-size digital loop is adopted in each channel, and the clock is recovered by phase interpolation from a shared reference. A complete optical-to-electrical (OE) link is built by integrating the proposed ORX with a high-speed Silicon Photonics (SiP) photodetector (PD). Measurements show that the proposed TIA has a transimpedance gain of 53 dB$\Omega $and a BW of 27 GHz. By integrating it with the SiP PD, the OE front-end (PD+TIA) achieves an input sensitivity of −7.7 dBm at 50 Gb/s and BER$ < 10^{-12}$. It features a power efficiency of 1.61 pJ/bit at a data rate of 64 Gb/s. The complete 50 Gb/s ORX achieves data recovery at a quarter rate of 12.5 Gb/s with an output jitter of 1.6 psrms, and has a 3.125 GHz clock with phase noise of −115.22 dBc/Hz at an offset frequency of 1 MHz. Sikai Chen, Mingyang You, Yunqi Yang, Leliang Li, Guike Li, Zhao Zhang 0004, Binhao Wang 0002, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu 0021, Nanjian Wu, Yong Chen 0005, Ninghua Zhu, Nan Qi 0002 |
IEEE Trans. Circuits Syst. I Regul. Pap. | 19 |