Comparators have been optimized for quick decision-making and reduction of dynamic power consumption through years of research by incorporating strong positive feedback latches. However, these advancements can make double-tail dynamic comparators more susceptible to single-event effects (SEEs). In this work, we present a new comparator design that is hardened against these radiation effects. The proposed design is a modified version of a low-voltage, low-power double-tail comparator, designed in a 180 nm technology node, and it can achieve high levels of SEE tolerance with an acceptable degree of trade-off in area, delay, and power consumption. The proposed comparator is shown to have superior SEE tolerance compared to a radiation-hardened conventional double-tail comparator with a similar electrical performance designed in the same technology node, and the proposed design’s functionality is proven by post-layout simulations across extreme simulation corners, combining process corners with temperature and supply voltage variations.

The memristor, as a cutting-edge nanodevice, has been studied for decades and gives rise to a wide range of applications across various fields. Although small signal analysis are crucial in circuit design and memristors exhibit unique Alternating Current (AC) features such as memimpedance, extensive research and reliable AC models are still lacking. This paper presents a memristor small-signal AC model that captures memimpedance effect by statistical modelling the complex impedance as a function of stimulus frequency and resistive state (RS). The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. The proposed model can support small-signal analysis for hybrid CMOS/memristor circuits and systems, providing more realistic memristor AC behaviours. The modelled memimpedance signature is expected to enable more emerging circuit applications.

The development of non-volatile Compute-In-Memory (nvCIM) technology has demonstrated significant potential in addressing the data movement and Multiply-and-Accumulate (MAC) bottlenecks in machine learning algorithms by enabling parallel analog Vector-Matrix Multiplication (VMM) operations directly within memory arrays. In this work, we introduce SPIKA, a fully integrated RRAM-CMOS chip designed for neural network acceleration. The key innovation of SPIKA lies in its ability to efficiently transfer input signals to output signals with minimal circuit overhead. The VMM operation is performed in the time domain, with the dot product accumulated on a switched capacitor, eliminating the need for high-resolution, power-intensive data converters. Implemented using commercially available 180nm technology, SPIKA operates on a 64×128 crossbar and utilizes 4-bit inputs, ternary weights, and 5-bit outputs. The chip is evaluated on the MNIST dataset, achieving a peak throughput of 1092 GOPS and an energy efficiency of 195 TOPS/W.

This paper provides a case study for enhancing Threshold Logic (TL) performance by exploiting the back-gate bias control offered by 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology across three process corners and five temperatures under transient noise. The paper demonstrates how back-gate biasing changes the threshold voltage and reduces the offset from 500µV to 400µV. Moreover, the improvement of 200µV in symmetric offset range and 100µV in input resolution are observed in comparison to conventional biasing. These improvements come at the cost of increased energy dissipation at temperatures higher than 27°C. The accuracy detection is slightly better under conventional biasing with an improvement of 30µV differential input range at 125°C. The back gate biasing results in a marginal shift of the graph by 0.03% at −55°C to a maximum of 8% at 125°C in comparison to the conventional biasing.

This paper compares the cross-technology performance of an improved Adiabatic Capacitive Neuron (ACN) design variant. Performance is compared across three commercially available CMOS technologies: two bulk 180nm and 130nm and a 22nm, ultra-low-power Fully-Depleted Silicon-On-Insulator (FDSOI) technology for extreme-edge neuromorphic computing. For comparison, we implement an ACN that is functionally equivalent to a software-trained Artificial Neuron (AN) with binary inputs and outputs, as well as positive, real-valued weights. The paper also demonstrates how back-gate biasing in FDSOI can be used to manipulate the threshold voltage and thus reduce threshold and leakage losses, further enhancing the energy performance of the adiabatic components of the ACN. Simulation results demonstrate that the 22nm technology node dramatically outperforms its 180nm and 130nm counterparts in energy savings, especially at frequencies of 10MHz and above. At 100MHz the synapse energy savings are 4.8x and 3.5x, while the threshold logic savings are 10x and 4.5x when compared to 180nm and 130nm technologies respectively.

To address memory throughput challenges in contemporary computing systems, content-addressable memories (CAMs) and dually-addressable memories (DAMs) are implemented to enable fast search operations. However, current FPGA implementations severely lack dual addressability with high resource costs. In this paper, we present a resource-efficient Block RAM (BRAM)-based DAM architecture on FPGA to enable effective database manipulations without data duplication. An example design of size 8×512×36 bits is implemented on Xilinx Virtex-7 FPGA with 4 BRAM36, 683 LUTs, and 248 FFs, reaching a 100% BRAM to DAM efficiency.

Content addressable memory is popular in intelligent computing systems as it allows parallel content-searching in memory. Emerging CAMs show a promising increase in bitcell density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a$64\times 64$array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take three clock cycles. Its worst average energy for data match is reported to be 1.71fJ/bit-search and the worst average energy for data miss is found at 4.69fJ/bit-search. The prototype is simulated and fabricated in 0.18um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.

The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

The AI revolution shows the ever increasing performance demands of AI applications like Deep Neural Networks DNNs which consist of tens of layers and do computations on tens of millions of data weights [1]. Conventional Von Neumann architectures are currently struggling to meet these emerging performance demands with deep memory hierarchies to bridge the processor-memory performance gap [2]. Emerging technologies (like RRAMs) have meanwhile shown a real promise to address the increasing challenges of the conventional computing technology. While the main direction of research is focussing on exploiting the analogue memory attributes of RRAMs specially for analogue computing crossbars [3], this paper focuses on a different perspective of building high-density and digital-friendly RRAM-based memory that is a good alternative to the SRAM-based Last-Level Caches LLCs. This digital RRAM-based memory with conventional 1T1R bit-cells is proposed to be an on-chip gigantic data reservoir, with much higher density than SRAMs, to bridge the memory gap. The paper also shows that the digital RRAM-based memory is capable of doing robust bit-line compute which opens the door for digital in-memory computing architectures that can mitigate the Von Neumann bottleneck while adopting RRAM’s high-density promise. Unlike analogue RRAM crossbars, RRAMs’ digital in-memory computing capability should inherit the large scalability and the fast time-to-market of the digital domain with less engineering effort for optimisation as there is no need any more to build DACs and ADCs.

Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.

One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at$100^{o}C$across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1 MHz indicates a æ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a æ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.

In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendly- associative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (≈4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 μW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.

Detecting neuronal activity for rehabilitation/assistive devices is an example of extreme edge computing, featuring stringent requirements for data bandwidth from implantable acquisition system, low-power consumption and ideally also low latency. Recently, we proposed a neural recording system which detects neural spikes directly on the signals collected from electrophysiological probes. The system achieves power efficiency by utilising a combination of integrative sensing and ultra-fine offset compensation. A central component of this design is a memristive load, which is utilised as a trimming device along the differential branches of the core amplifier, ultimately allowing system offset tuning with μν precision. Previous work has assumed that the memristive device features a linear, or nearly-linear current-voltage (IV) characteristic. In this paper, we study the impact of memristor IV non-linearity on the effective gain and offset compensation capability of the system. Results show that the non-linearity experimentally measured from our in-house metal-oxide memristor technology only induces a small gap between nominal resistive state and static RS (as reflected on the IV). This leads to a very small degradation of gain (≈ 2.5%) and offset compensation (≈ 50% increased offset tuning sensitivity), but very crucially proves that introducing IV non-linearity does not materially change either the extreme offset trimming precision or the overall performance. This was the last conceptual bottleneck identified before practical implementation and it has now been overcome.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

Memristor crossbar arrays offer a novel new approach for designing high density non-volatile memory; however, precise measurement of resistive crossbar elements requires parallel current sensing capability not found in existing instruments. To provide this capability, we have designed and built an FPGA-based crossbar control instrument with independent per-channel biasing and measuring. In this paper, we cover the architecture of this new instrument, its operation and interface, and the results of testing conducted on the instruments pulse driver circuitry.

In this demonstration, we present a new electro-forming process, along with a new instrument to support this procedure. Memristor arrays will be available for the user to electroform, write, and read the resulting resistive state of the devices.

An important cornerstone of data processing is the ability to efficiently capture structure in data and perform data classification. More recently, memristive technologies enabled the incorporation of continuous tuneable resistive elements directly in hardware, thus increasing the efficiency of reconfigurable systems power and area-wise. Memristors are a promising candidate for reconfigurable circuits capable of carrying out classification with physical computing, such as dot-product vector multiplication and accumulation technique. In this work, we demonstrate a novel proof-of-concept memristor-based Digital-In-Analogue-Out logic circuit and present preliminary results highlighting the effect of non-uniform non-linear memristor IV characteristics that result in device-to-device behavioural variation.

The continuous maturation of novel nanoelectronic devices exhibiting finely tuneable resistive switching is rekindling interest in analogue-domain computation. Regardless of domain, a useful computational module is the arithmetic-logic unit (ALU), which is capable of performing one or more fundamental mathematical operations (typical example: addition and subtraction). In this work we report on a design for an analogue ALU (aALU) capable of performing barrel addition and subtraction (i.e. ADD/SUB in modular arithmetic). The circuit only requires 5 minimum-size transistors and 1 capacitor. We show that our aALU is in principle capable of handling 5 bits of information using a single input/output wire. Core power dissipation per operation is estimated to peak at ≈ 59 f J (input operand-dependent) in TSMC's 65 nm technology.

We demonstrate an environmental control system for testing Resistive Random Access Memory technologies under accurately controlled humidity and temperature. The demonstrated system compresses the functionality of existing environmental control systems into a low cost, desktop-size solution, aimed at providing results quickly and with minimum installation and running overheads.

Environmental conditions can greatly affect the performance of semiconductor devices. Great sophistication has thus gone into developing versatile systems that allow benchmarking of operating characteristics under a variety of temperature and humidity conditions. Recently, Resistive Random Access Memory (RRAM) technologies, also known as memristors, have received a lot of attention for memory and computing applications. This interest is showcased by several reports on technology and applications developments, as well as developments on the underpinning infrastructure, i.e. models and characterization tools, that renders such technologies useful. Several international research groups and companies are nowadays using ArC One™, a versatile instrument that allows en masse characterization of RRAM technologies, as has been presented previously in several demo sessions at ISCAS. In this work, we present a newly developed module that expands ArC One™ capabilities through incorporating an environmental control system. The proposed module condenses the functionality of significantly larger, more complex and higher cost systems into a low cost, small form-factor and user friendly desktop-operated device. The system allows for temperature, atmospheric composition and humidity control and can be used for studying the impact of such settings on the electrical characteristics of RRAM technologies.

With the recent advances of the emerging memories technologies, research are able to implement novel circuits, systems and computer architectures towards the design of high-performance and low-power electronic systems able to accelerate and/or optimize the functionality of many computer workflows. One emerging technology, the ReRAM/memristor is gathering attention due to its inherent advantages for logic and memory computing systems. At the same time, CMOS circuit design seems to have reached a limit, where easily optimized circuit solutions cannot be found. Thus, further research towards novel logic gate families, such as Threshold Logic Gates (TLGs), a logic family known for its high-speed and low power consumption, is needed. Although many implementation concepts of TLG circuit are using memristors, few of these implementations are based on physical ReRAM devices. In this work we are proposing a memristor-based threshold logic gate design towards the optimization of computer workflows. The presented results include a physical implementation of the proposed circuits which supports the concept of memory-based reconfigurable computing circuits and systems.

The ability to read brain activity across large swathes of cortex at very high resolution both spatially and temporally is a holy grail objective of modern neuroscience. In this endeavour, the minuteness of neural signals arriving from needle probes (10s to 100s of μV) poses a significant challenge, typically solved using high spec amplifiers. However, when the objective is to detect neural spikes the input signals of interest are inherently sparse, and much energy is spent amplifying data points that will be ultimately discarded. In this work we propose that a possible solution is to distance ourselves from the need to amplify the neural waveforms, and instead opt for performing threshold detection directly on the input signal; which is often sufficient to detect neural spiking. We thus present a high sensitivity threshold detection circuit concept that uses its offset voltage as the reference threshold and thus directly transforms differential input signal samples into digital values. The use of memristive devices within the design allows us to finely tune the detector's offset voltage, thus ensuring sufficient operational flexibility. Using SPICE simulations we demonstrate an exemplar design built using our concept. First we shown its functionality and then we proceed to examine how: i) mismatch at strategically chosen devices affects the amplifier's offset voltage and ii) changing the resistive state of the memristive devices involved helps the designer control the offset voltage.

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include threshold logic and receptive field based classifiers that are presented within the context of a unified perspective.

In this demo we present a comprehensive solution for benchmarking the multibit capabilities of resistive memory cells using sequential programming pulses. The algorithm is presented through a rich graphical user interface that allows the user to fully tune the benchmarking parameters.

In this work we present an evaluation routine aimed towards assessing the multibit capability of Resistive Random Access Memory (RRAM) technologies. We illustrate a characterization methodology for the maximum possible exploitation of the resistive states of a RRAM cell. Our characterization routine consists of a three phase algorithm: during the first it infers the polarity needed to induce a change in the device's conductance; the second stabilizes the resistive states of the device into a baseline resistance and during the third a sequence of pulses of increasing amplitude is used to determine the actual resistive states. This technology-agnostic methodology allows for efficient and high resolution partitioning of the cell's resistive operating range allowing them to operate in a truly analogue fashion. Demonstrating the maximum potential of RRAM cells in terms of closely packed resistive states can open new avenues for research in non-volatile memories, reconfigurable electronics and neuromorphic applications.

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

A flexible, versatile, and visually rich memristor crossbar simulator is presented in this paper. The system is represented by a Python graphical user interface (GUI) and memristor simulator engine which can instantiate crossbars of any size made out of any available memristor model. This system serves as an education tool, allowing the user to experiment with memristors in a crossbar configuration.

The sensitivity of a recently proposed spike detector exploiting the volatile properties of memristive device is optimised. A 200 nm × 200 nm TiOx memristive device in volatile region is biased with sub-threshold, unipolar and bipolar neural events. The input neural signal is pre-processed using different amplification settings. The resistive state response of the test device in response to the input events is analysed and it is found that inclusion of events in positive polarity leads to subsequent increase in the number of false events when benchmarked against state-of-the-art spike detector (template matching system). The performance of the system is thereafter optimised by determining optimum amplification settings and employing an offset such that positive polarity events in the input signal are minimised.

We demonstrate a desktop platform which has the ability of modeling ReRAM TiO2samples in a highly automated manner. The system consists of a bespoke RRAM characterization instrument that hosts packaged RRAM devices and is operated via a PC. The system's python-based software includes a module that automatically applies strategically chosen sequences of pulses to a test device and then extracts the suitable parameter values for a resistive switching model from the elicited response.

The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a `template pixel' (texel) circuit combining CMOS and memristive devices to perform on-line spike sorting through template matching. We show through simulation how the texel is capable of comparing an input voltage against a stored (in the memristors) value and converting the degree of matching between input and stored pattern into a current. We further illustrate the fundamental texel design space that includes tuning it to a different preferred input voltage and controlling the sharpness of the tuning. Finally, we estimate that even in an unoptimised technology and design a texel array capable of recognising three different 10-point patterns will consume a very promising maximum of 3.15 μW for a footprint of approx. 500 μm2.

We demonstrate a desktop platform which has the ability of fully characterizing RRAM crossbar arrays while not compromising on ease-of-use. The setup consists of our bespoke PCB system connected to a local PC (laptop), on which a Pyhton interface allows the user to directly interact with individual RRAM cells packaged in either crossbar or stand-alone configurations. The platform is capable of current-compliant forming among other exotic pulsing schemes, used for exposing IV and switching characteristics or utilising the devices for a wide range of applications. These operations can be applied on one, or several cells, in an automated fashion, drastically accelerating data acquisition.

In recent years, biologically inspired systems, which emulate the nervous system of living beings, are becoming more and more requested due to their ability to solve ill-posed problems such as pattern recognition or interaction with the external environment. By virtue of their nanoscaled size and their tunable conductance, memristors are key elements to emulate high-density networks of biological synapses that regulate the communication efficacy among neurons and implement learning capability. We propose a TiN/ HfO2/Ti/TiN memristor as artificial synapse for neuromorphic architectures. The device can gradually change its conductance upon application of proper electrical stimuli. More specifically, it features gradual potentiation and depression when stimulated by trains of identical potentiating or depressing spikes, which are easy to be implemented on-chip. Moreover, we demonstrate that the memristor conductance can be regulated according to the delay time between two spikes incoming to the device terminals. This regulation of memristor conductance implements the typical biological learning process named Spike-Time-Dependent-Plasticity (STDP). Finally, collected STDP data were used to simulate a simple fully connected Spiking Neural Network (SNN) for pattern recognition.

The effects of key operating parameter on the practical operation of a recently proposed memristor-based neuronal activity sensor are investigated. A test memristor device is repeatedly subjected to a reference neural recording input signal that has been pre-processed using different settings. The resulting changes in the ability of the device to capture and store neuronal activity as resistive state transitions are assessed. It is found that resistive switching saturation is an important performance limiting factor, combatable by resetting the memristor. Higher desired sensitivity (ability to detect less prominent features in the neural waveform) necessitates more frequent resets.

A hardware-friendly, ultra-low voltage read-out technique for multi-level RRAM technologies inspired by the dithering techniques from image processing is proposed and studied. We lay out the fundamental principles behind our adaptation of the approach, present results from hardware tests, carry out sensitivity analysis through simulations in order to study its l imitations. Successful discrimination between a few resistive state levels is shown at a read-out voltage of just 10 mV, thus proving the concept.

A practical system for reading out from linear, multi-level, selectorless Resistive Random Access Memory (RRAM) arrays based on a Trans-Impedance Amplifier (TIA) approach is presented and studied. SPICE simulation of the core of the system is performed in order to extract predicted sensitivity to error factors such as non-zero TIA offsets and access resistance. A physical implementation of the system is then tested on a small, 12 × 12 reference array and measured results show its ability to decode absolute resistive states in the range of 1 kΩ–220 kΩ within ≈ 11% tolerance.

Event-based computation is a well-established way of reducing the complexity of neural modelling, often used as an enabling step towards the simulation of large neuronal ensembles. Recently, the advent of the physical memristor has provided the scientific community with a stand-alone nanoelectronic device that exhibits strongly `synapse-like' behaviour and can be used in general neural modelling. In this paper we review the suitability of the most common, basic memristor models for use in tandem with event-based techniques and conclude that neither of them can support spike timing-dependent plasticity (STDP); a staple of modern neuroscience.We then identify the necessary attributes of any model that can enmesh STDP into event-based computation and present measured results evidencing that solid-state TiO2-based memristors intrinsically support such feature.

We demonstrate a practical application of memristors in a cross-bar memory array. The full set-up consists of only a PC, an mBED microcontroller and a PCB hosting external components and the memristor cross-bar chip. The system can be used for general purpose memory storage, but in this case we use it as a binary image storage device. A MATLAB interface allows the user to load a binary image into the memory and observe the resulting internal memory states of each memristor in the array along with key performance metrics describing the speed and degree of success of the memory `write' operation.

This paper proposes a novel, octagonal shaped CMOS image sensor (CIS) array for use in tandem with colored LED illumination and a corresponding, innovative pixel scanning method. The octagonal shape of the pixel array allows the CIS to make near-optimal use of silicon real estate by matching the perimeter of the pixel array to the focal plane area of lenses used in Wireless Capsule Endoscopies (WCE). Providing illumination by sequencing different-colored LEDs allows the system to reuse the same pixels to capture different colors at different times, thus removing the need for manufacturing a Color Filter Array (CFA) and effectively trading temporal for spatial resolution. The system was designed with AMS 0.35µm 2P4M CMOS technology. The simulated system consumes 1.06 mW from a 2.5 V supply at 2.217 frames/sec operation.