Demo Data from VLDB 2026 / reviewers in the wild / expert
Emmanouil Pissadakis
dblp:183/4853 · also Manolis Pissadakis
· DBLP profile ↗
4ranked-venue papers
1as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 68% Reconfigurable computing and FPGAs · 32% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Bioinformatics and computational biology · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › processing-in-memory
near-memory processing |
0.4 | 1 | 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference · FPGA 2020 |
Bioinformatics and computational biology › phylogenetics
phylogenetic inference |
0.1 | 1 | 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference · FPGA 2020 |
Memory systems › memory access optimization
data movement reduction |
0.1 | 1 | 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference · FPGA 2020 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.1 | 1 | 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference · FPGA 2020 |
Reconfigurable computing and FPGAs › FPGA-based emulation
multi-FPGA emulation |
0.1 | 1 | 2020 | Near-memory Acceleration for Scalable Phylogenetic Inference · FPGA 2020 |
Methods — techniques the papers use, named apart from their topics
near-memory computation units · 0.9disaggregated memory · 0.9data-allocation scheme · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Scalable Phylogeny Reconstruction with Disaggregated Near-memory ProcessingabstractDisaggregated computer architectures eliminate resource fragmentation in next-generation datacenters by enabling virtual machines to employ resources such as CPUs, memory, and accelerators that are physically located on different servers. While this paves the way for highly compute- and/or memory-intensive applications to potentially deploy all CPUs and/or memory resources in a datacenter, it poses a major challenge to the efficient deployment of hardware accelerators: input/output data can reside on different servers than the ones hosting accelerator resources, thereby requiring time- and energy-consuming remote data transfers that diminish the gains of hardware acceleration. Targeting a disaggregated datacenter architecture similar to the IBM dReDBox disaggregated datacenter prototype, the present work explores the potential of deploying custom acceleration units adjacently to the disaggregated-memory controller on memory bricks (in dReDBox terminology), which is implemented on FPGA technology, to reduce data movement and improve performance and energy efficiency when reconstructing large phylogenies (evolutionary relationships among organisms). A fundamental computational kernel is the Phylogenetic Likelihood Function (PLF), which dominates the total execution time (up to 95%) of widely used maximum-likelihood methods. Numerous efforts to boost PLF performance over the years focused on accelerating computation; since the PLF is a data-intensive, memory-bound operation, performance remains limited by data movement, and memory disaggregation only exacerbates the problem. We describe two near-memory processing models, one that addresses the problem of workload distribution to memory bricks, which is particularly tailored toward larger genomes (e.g., plants and mammals), and one that reduces overall memory requirements through memory-side data interpolation transparently to the application, thereby allowing the phylogeny size to scale to a larger number of organisms without requiring additional memory. Nikolaos Alachiotis 0001, Panagiotis Skrimponis, Emmanouil Pissadakis, Dionisios N. Pnevmatikatos |
ACM Trans. Reconfigurable Technol. Syst. | 3 |
| 2020 | Near-memory Acceleration for Scalable Phylogenetic InferenceabstractPhylogenetics study the evolutionary history of a collection of organisms based on observed heritable molecular traits, finding practical application in a wide range of domains, from conservation biology and epidemiology, to forensics and drug development. A fundamental computational kernel to evaluate evolutionary histories, also referred to as phylogenies, is the Phylogenetic Likelihood Function (PLF), which dominates the total execution time (by up to 95%) of widely used maximum-likelihood phylogenetic methods. Numerous efforts to boost PLF performance over the years mostly focused on accelerating computation; since the PLF is a data-intensive, memory-bound operation, performance remains limited by data movement. In this work, we employ near-memory computation units (NMUs) within a FPGA-based computing environment with disaggregated memory to alleviate the data movement problem and improve performance and energy efficiency when inferring large-scale phylogenies. NMUs were deployed on a multi-FPGA emulation platform for the IBM dReDBox disaggregated datacenter prototype. We find that performance and power efficiency improves by an order of magnitude when NMUs compute on local data that reside on the same server tray. This is achieved through an efficient data-allocation scheme that minimizes inter-tray data transfers (remote-data movement) when computing the PLF. More specifically, we observe up to 22x better FLOPS performance and 13x higher power efficiency (FLOPS/Watt) over the more traditional, accelerator-as-a-coprocessor model, which requires explicit remote-data transfers between disaggregated memory modules and accelerator units. Nikolaos Alachiotis 0001, Panagiotis Skrimponis, Emmanouil Pissadakis, Sundeep Rangan, Dionisios N. Pnevmatikatos |
FPGA | 3 |
| 2018 | ReFiRe: Efficient Deployment of Remote Fine-Grained Reconfigurable AcceleratorsabstractThe need for specialized hardware acceleration in today's computing platforms is well established, due to power and efficiency reasons. Broadening an accelerator's scope of application is highly desirable, but requires a finer-grained architecture with basic primitives, which inevitably exhibits increased communication and synchronization requirements. In disaggregated-computing environ-ments, where data transfers between remote nodes are realized via datacenter-wide packet exchanges, reducing communication and synchronization is a prerequisite for the effective employment of remote acceleration. To this end, we present ReFiRe (Remote Fine-grained Reconfigurable acceleration), a generic deployment framework with native support for partial reconfiguration that allows to considerably reduce communication needs between a processor and remote accelerators. This is achieved by shifting control flow, partial reconfiguration, and execution decisions to the remote side through arbitrarily long instructions that encapsulate complex sequences of operations and their re-spective synchronization requirements. ReFiRe outperforms an SDSoC-generated accelerator system that employs the same accelerator cores to boost performance of a genomics application that detects positive selection. Emmanouil Pissadakis, Nikolaos Alachiotis 0001, Panagiotis Skrimponis, Dimitris Theodoropoulos 0001, Thanasis Korakis, Dionisios N. Pnevmatikatos |
FPT | 1 |
| 2016 | mCluster: A Software Framework for Portable Device-Based Volunteer ComputingabstractRecent market forecasts predict that the portable computing trend will vastly spread, as by 2020 there will bemore than 3 billion LTE device users worldwide. Motivated by this fact, many companies and research institutes have already launched research projects that utilize portable devices, voluntarily provided by users, to perform the required computations. Many such projects employ Berkeley's BOINC middleware, since it can support a large variety of stationary and mobile devices. However, currently available BOINC high-level APIs, either do not support portable devices or lack advanced processing capabilities (such as inter-node task dependencies) and/or easiness of use. To resolve these issues, we propose the mCluster software framework for application execution powered by the BOINC middleware on portable devices. mCluster adopts a task-based programming model that requires simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. To evaluate our framework, we have have mapped a scientific application from the neuroscience domain on an small-scaled network of portable devices. mCluster significantly reduces the required programming effort and complexity to efficiently map BOINC-powered applications with task dependencies on portable devices compared to previous approaches. Dimitris Theodoropoulos 0001, Grigorios Chrysos 0001, Iosif Koidis, George Charitopoulos, Emmanouil Pissadakis, Antonis Varikos, Dionisios N. Pnevmatikatos, Georgios Smaragdos, Christos Strydis, Nikolaos A. Zervos |
CCGrid | 5 |