Event-driven cameras are well suited for always-on edge vision, but forwarding all events creates unnecessary overhead. Events outside user-defined ROIs are semantically irrelevant, while many ROI events arise from background motion, lighting changes, or sensor noise rather than meaningful activity. We propose SENTRY, a near-sensor pipeline that addresses both issues through hierarchical spatial reasoning. A coarse spike-rate gate discards frames with low ROI activity, while a spatially-aware confirmation stage compares each region’s activity against the global background rate to suppress diffuse noise. Evaluated on a real indoor surveillance sequence, SENTRY achieves +64% precision and − 57% false positive rate relative to a global spike-rate baseline, targeting resource-constrained, always-on platforms where energy efficiency and rapid response must be achieved simultaneously.

We present BISen, a framework for efficient and reliable convolutional neural network (CNN) inference on battery-free, energy-harvesting IoT sensor nodes. Battery-powered deployments suffer from limited lifetimes, high replacement costs, and environmental impacts, problems that will intensify as IoT scales to billions of devices. Energy-harvesting nodes remove batteries but face intermittent power, resulting in frequent failures that corrupt the intermediate CNN state, require costly checkpointing and rollback, and amplify non-volatile memory (NVM) traffic under tight on-chip memory constraints, leaving little harvested energy for useful sensing and inference. BISen introduces a reactive intermittent execution model for CNN workloads on off-the-shelf ultra-low-power microcontrollers. An energy-aware state machine with a safe-stop mechanism halts execution before brownout, while selective checkpointing preserves only the minimal CNN state needed for forward progress. This enables seamless resumption across power cycles while sharply reducing NVM reads/writes and memory-access overheads. Across two commercial MCU+radio platforms, three real harvested power traces, and nine CNNs, BISen cuts NVM operations by up to 86.4%, reduces standby/load/store operations by up to 94.1%, 94.5%, and 90.7%, and improves sensing throughput by about 1.3−1.4× compared to a state-of-the-art reactive baseline under the same energy budget, enabling long-lived, battery-free, carbon-aware IoT deployments.

This paper presents ResISC, an RNS-based integrated sensing and computing architecture enabling efficient edge AI. ResISC platform features (i) an in-sensor residue encoder converting images directly to RNS in the analog domain, (ii) an energy-efficient RNS-based processing-near-sensor CNN accelerator utilizing SOT-MRAM, and (iii) an innovative mixed-radix unit for efficient activation operations. By employing selective channel deactivation, ResISC reduces computation overhead by up to $89 \%$, while achieving a $3.4 \times$ improvement in power efficiency and up to a $71 \times$ reduction in execution time compared to processing-in-MRAM platforms. Experiments on various datasets demonstrate that ResISC achieves competitive accuracy levels (up to $94.63 \%$ on CIFAR-10) with minimal degradation, making it an ideal solution for power-constrained, real-time edge applications.

This paper proposes an analog-domain watermarking approach implemented directly in CMOS sensors. By embedding the watermark at the readout stage before ADC, we achieve a robust, tamper-resistant mechanism with minimal impact on image quality. Modifications to the column amplifier architecture and a secure pattern generator enable effective watermark embedding. Experimental results on a 64×64 pixel array showcase high watermark detection rates (> 85%) under various attacks.

This paper introduces Stochastic Intermittent Computing (STIC), a framework that integrates intermittent computing (ImC) and stochastic computing (SC) to enable always-on sensing in energy-harvested systems. STIC dynamically adjusts computational precision based on available energy, eliminating the need for non-volatile memory checkpointing traditionally used in ImC systems. By adapting precision in real-time, STIC ensures continuous operation even under severe power fluctuations, significantly improving energy efficiency and system resilience. Evaluation results demonstrate that STIC achieves substantial reductions in area, power, and energy consumption owing to the simplicity of SC and its tolerance to aggressive voltage scaling. Evaluations across multiple neural networks and charging traces confirm that STIC enables robust, low-power edge intelligence for resource-constrained environments.

RL-SEP is a reinforcement learning scheduler that optimizes neural network execution in energy-harvesting devices. By dynamically selecting quantization levels and early exit points, it improves active operation time by up to 11% over the reactive method while achieving 136% better accuracy-to-energy ratio and maintaining higher energy reserves. Testing on ResNet-18 and DenseNet-121 shows robust performance across various harvesting sources.

This paper proposes a high-performance and energy-efficient optical near-sensor accelerator for vision applications, called Lightator. Harnessing the promising efficiency offered by photonic devices, Lightator features innovative compressive acquisition of input frames and fine-grained convolution operations for low-power and versatile image processing at the edge for the first time. This will substantially diminish the energy consumption and latency of conversion, transmission, and processing within the established cloud-centric architecture as well as recently designed edge accelerators. Our device-to-architecture simulation results show that with favorable accuracy, Lightator achieves 84.4 Kilo FPS/W and reduces power consumption by a factor of ~24× and 73× on average compared with existing photonic accelerators and GPU baseline.

With the rise of tiny IoT devices powered by machine learning (ML), many researchers have directed their focus toward compressing models to fit on tiny edge devices. Recent works have achieved remarkable success in compressing ML models for object detection and image classification on microcontrollers with small memory, e.g., 512kB SRAM. However, there remain many challenges prohibiting the deployment of ML systems that require high-resolution images. Due to fundamental limits in memory capacity for tiny IoT devices, it may be physically impossible to store large images without external hardware. To this end, we propose a high-resolution image scaling system for edge ML, called HiRISE, which is equipped with selective region-of-interest (ROI) capability leveraging analog in-sensor image scaling. Our methodology not only significantly reduces the peak memory requirements, but also achieves up to 17.7× reduction in data transfer and energy consumption.

Targeting vision applications at the edge, in this work, we systematically explore and propose a high-performance and energy-efficient Optical In-Sensor Accelerator architecture called OISA for the first time. Taking advantage of the promising efficiency of photonic devices, the OISA intrinsically implements a coarse-grained convolution operation on the input frames in an innovative minimum-conversion fashion in low-bit-width neural networks. Such a design remarkably reduces the power consumption of data conversion, transmission, and processing in the conventional cloud-centric architecture as well as recently-presented edge accelerators. Our device-to-architecture simulation results on various image data-sets demonstrate acceptable accuracy while OISA achieves 6.68 TOp/s/W efficiency. OISA reduces power consumption by a factor of 7.9 and 18.4 on average compared with existing electronic in-/near-sensor and ASIC accelerators.

Battery-powered IoT devices face challenges like cost, maintenance, and environmental sustainability, prompting the emergence of batteryless energy-harvesting systems that harness ambient sources. However, their intermittent behavior can disrupt program execution and cause data loss, leading to unpredictable outcomes. Despite exhaustive studies employing conventional checkpoint methods and intricate programming paradigms to address these pitfalls, this paper proposes an innovative systematic methodology, namely DIAC. The DIAC synthesis procedure enhances the performance and efficiency of intermittent computing systems, with a focus on maximizing forward progress and minimizing the energy overhead imposed by distinct memory arrays for backup. Then, a finite-state machine is delineated, encapsulating the core operations of an IoT node, sense, compute, transmit, and sleep states. First, we validate the robustness and functionalities of a DIAC-based design in the presence of power disruptions. DIAC is then applied to a wide range of benchmarks, including ISCAS-89, MCNS, and ITC-99. The simulation results substantiate the power-delay-product (PDP) benefits. For example, results for complex MCNC benchmarks indicate a PDP improvement of 61%, 56%, and 38% on average compared to three alternative techniques, evaluated at 45 nm.

The surge in the number of normally-off power-constraint Internet of Things (IoT) devices in recent years has amplified the demand for high-performance and energy-efficient in-memory computing architectures built on top of various non-volatile memories. Magneto-Electric Field Effect Transistors (MEFETs) have presented compelling design features suitable for logic and memory integration as an emerging post-CMOS FET. These include high-speed switching, minimal power usage, and non-volatility. This work introduces a new in-memory computing architecture designed for edge applications, leveraging emerging MEFETs. The proposed architecture enables the execution of both Boolean logic operations and Binary Content Addressable Memory (BCAM) operations within a single cycle. Furthermore, the energy consumption during the write operation of the proposed cell is optimized by introducing a new write circuitry. The outcomes of our device-to-architecture evaluation reveal approximately 43.5% and 96.9% reduction in read and write energy consumption, respectively, compared to the counterpart non-volatile memories. At the application level, the proposed architecture is applied to implement Binary Neural Networks (BNNs) based on AlexNet and VGG16. Our results showcase a decrease of approximately 54% in the overall energy consumption when implementing these networks using the proposed design compared to non-volatile in-memory computing designs.

The widespread adoption of vision sensors raises significant security and privacy concerns. In this paper, we present RACSen as a novel architecture that can increase the security and efficiency of conventional image sensors. RACSen leverages the intricate mathematical properties of the residue number system (RNS) with analog scrambling techniques to create a sophisticated dual-layered encryption mechanism. Incorporating RNS within analog-to-digital converters further strengthens security by mitigating replay attacks and preserving data transmission integrity and confidentiality. Our results demonstrate exceptional encryption, with a perfect pixel change rate of 99.90 and high intensity change of 45.77. This offers robust image data protection with minimal overhead of 11.11%.

Wireless Sensor Networks (WSN) are integral to diverse applications, ranging from environmental monitoring to urban smart infrastructure. In the realm of WSNs, security remains a critical challenge owing to the complex nature of the sensor environment. As a result, WSN security has become a research focus in recent years. In this paper, we introduce ChaoSen, a novel image sensor system incorporating analog chaotic circuits within the sensor, thereby enhancing the overall system security. The system utilizes a scrambler module, which intricately intertwines with the chaotic encryption process, to reduce the predictability of pixel values and enhance the security of the system. Comparative evaluations demonstrate that the system achieves an NPCR value of 99.5562% and a UACI of 35.81900%, indicating high sensitivity to input changes and significant alteration in pixel intensity. Our approach also demonstrates its resilience against common cyber attacks, balancing enhanced security with resource efficiency.

Convolutional neural networks (CNNs) have been gaining popularity in recent years, and researchers have designed specialized architectures to speed up the inference process. However, despite the promising potential of processing near-/in- sensor architectures actively explored in the visual Internet of Things, there is still a need to develop a behavior-level simulator to model performance and facilitate early design exploration. This article proposes a stand-alone simulation platform for processing-in-pixel (PiP) systems, namely, PiPSim. It offers a flexible interface and a wide range of design options for customizing the efficiency and accuracy of PiP-based accelerators using a hierarchical structure. Its organization spans from the device level, e.g., memory technology, upward to the circuit level, e.g., compute-add on architecture, and then to the algorithm level, e.g., DNN workloads. PiPSim realizes instruction-accurate evaluation of circuit-level performance metrics as well as learning accuracy at run-time. Compared to SPICE simulation, PiPSim achieves over 25$000\times $speed-up with less than a 2.5% error rate on average. Furthermore, PiPSim can optimize the design and estimate the tradeoff relationships among different performance metrics.

In this work, we propose a Parallel Processing-In-DRAM architecture named P-PIM leveraging the high density of DRAM to enable fast and flexible computation. P-PIM enables bulk bit-wise in-DRAM logic between operands in the same bit-line by elevating the analog operation of the memory sub-array based on a novel dual-row activation mechanism. With this, P-PIM can opportunistically perform a complete and inexpensive in-DRAM RowHammer (RH) self-tracking and mitigation technique to protect the memory unit against such a challenging security vulnerability. Our results show that P-PIM achieves ~72% higher energy efficiency than the fastest charge-sharing-based designs. As for the RH protection, with a worst-case slowdown of ~0.8%, P-PIM archives up to 71% energy-saving over the SRAM/CAM-based frameworks and about 90% saving over DRAM-based frameworks.

Recently, Intelligent IoT (IIoT), including various sensors, has gained significant attention due to its capability of sensing, deciding, and acting by leveraging artificial neural networks (ANN). Nevertheless, to achieve acceptable accuracy and high performance in visual systems, a power-delay-efficient architecture is required. In this paper, we propose an ultra-low-power processing in-sensor architecture, namely SenTer, realizing low-precision ternary multi-layer perceptron networks, which can operate in detection and classification modes. Moreover, SenTer supports two activation functions based on user needs and the desired accuracy-energy trade-off. SenTer is capable of performing all the required computations for the MLP's first layer in the analog domain and then submitting its results to a co-processor. Therefore, SenTer significantly reduces the overhead of analog buffers, data conversion, and transmission power consumption by using only one ADC. Additionally, our simulation results demonstrate acceptable accuracy on various datasets compared to the full precision models.

This paper presents Encode, a novel technique that merges active learning, model compression, and knowledge distillation to optimize deep learning models. The method tackles issues such as generalization loss, resource intensity, and data redundancy that usually impede compressed models' performance. It actively integrates valuable samples for labeling, thus enhancing the student model's performance while economizing on labeled data and computational resources. Encode's utility is empirically validated using SVHN and CIFAR-10 datasets, demonstrating improved model compactness, enhanced generalization, reduced computational complexity, and lessened labeling efforts. In our evaluations, applied to compressed versions of VGGll and AlexNet models, Encode consistently outperforms baselines even when trained with 60% of the total training samples. Thus, it establishes an effective framework for enhancing the accuracy and generalization capabilities of compressed models, which is especially beneficial in situations with limited resources and scarce labeled data.

Digital technologies have made it possible to deploy visual sensor nodes capable of detecting motion events in the coverage area cost-effectively. However, background subtraction, as a widely used approach, remains an intractable task due to its inability to achieve competitive accuracy and reduced computation cost simultaneously. In this paper, an effective background subtraction approach, namely NeSe, for tiny energy-harvested sensors is proposed leveraging non-volatile memory (NVM). Using the developed software/hardware method, the accuracy and efficiency of event detection can be adjusted at runtime by changing the precision depending on the application's needs. Due to the near-sensor implementation of background subtraction and NVM usage, the proposed design reduces the data movement overhead while ensuring intermittent resiliency. The background is stored for a specific time interval within NVMs and compared with the next frame. If the power is cut, the background remains unchanged and is updated after the interval passes. Once the moving object is detected, the device switches to the high-powered sensor mode to capture the image.

With the advent of Edge Intelligence (EI) devices, always-on intelligent and self-powered visual perception systems are receiving considerable attention. These emerging systems require continuous sensing and instant processing; however, the high energy data conversion/transmission of raw data and the limited available energy and computation resources make designing energy-efficient and low bandwidth CMOS vision sensors vital but challenging. This paper proposes a low-power integrated sensing and computing engine, namely Ocellus, which considerably decreases power costs of data movement/conversion and enables data/compute -intensive neural network tasks. Ocellus offers several unique features, including a highly parallel analog convolution-in-pixel scheme and reconfigurable filtering modes with filter pruning capability. These features realize low-precision ternary weight neural networks to mitigate the overhead of analog-to-digital converters and analog buffers. Moreover, the proposed structure supports a zero-skipping scheme to further reduce power consumption. Our circuit-to-application cosimulation results demonstrate comparable, even better, accuracy to the full-precision baseline on object classification tasks, while it achieves a frame rate of 1000 and efficiency of ~1.45 TOp/s/W.

In the Artificial Intelligence of Things (AIoT) era, always-on intelligent and self-powered visual perception systems have gained considerable attention and are widely used. Thus, this paper proposes TizBin, a low-power processing in-sensor scheme with event and object detection capabilities to eliminate power costs of data conversion and transmission and enable data-intensive neural network tasks. Once the moving object is detected, TizBin architecture switches to the high-power object detection mode to capture the image. TizBin offers several unique features, such as analog convolutions enabling low-precision ternary weight neural networks (TWNN) to mitigate the overhead of analog buffer and analog-to-digital converters. Moreover, TizBin exploits non-volatile magnetic RAMs to store NN’s weights, remarkably reducing static power consumption. Our circuit-to-application co-simulation results for TWNNs demonstrate minor accuracy degradation on various image datasets, while TizBin achieves a frame rate of 1000 and efficiency of ∼1.83 TOp/s/W.

This work proposes a new generic Single-cycle Compute-in-Memory (CiM) Accelerator for matrix computation named SCiMA. SCiMA is developed on top of the existing commodity Spin-Orbit Torque Magnetic Random-Access Memory chip. Every sub-array’s peripherals are transformed to realize a full set of single-cycle 2- and 3-input in-memory bulk bitwise functions specifically designed to accelerate a wide variety of graph and matrix multiplication tasks. We explore SCiMA’s efficiency by selecting a complex matrix processing operation, i.e., calculating determinant as an essential and under-explored application in the CiM domain. The cross-layer device-to-architecture simulation framework shows the presented platform can reduce energy consumption by 70.43% compared with the most recent CiM designs implemented with the same memory technology. SCiMA also achieves up to 2.5x speedup compared with current CiM platforms.

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.