Process variations have emerged as a severe performance bottleneck for advanced technology nodes. This paper investigates the delay behavior of a range of exact and incomplete parallel-prefix addition trees under variations, including speculative/approximate trees and trees with duplicated prefix nodes. The performance of a range of incomplete adder variants is investigated comparatively with conventional exact architectures at a 16-nm technology node. In order to capture variations generated from a range of process-dependent sources and their impact on delay characteristics, the analysis considers threshold voltage variations employing Spice-level simulations. Under nominal voltage and in the presence of threshold variations, incomplete architectures are found to still offer a smaller worst-case delay than their exact counterparts; similarly for a low-voltage scenario, where the supply voltage is reduced to 0.8 V. However, focusing on normalized delay variation, it is here found that incomplete-tree adders are more susceptible to variations as they show a wider delay spread than exact architectures around their respective mean values. As a remedy, it is shown that the number of stages in an incomplete adder can be used as a design parameter to investigate accuracy vs. variability-tolerance trade-offs. Furthermore, by duplicating delay-critical paths of prefix trees, worst-case delay and standard deviation reduce compared to the exact architectures.

Published in "IEEE Transactions on Emerging Topics in Computing, Volume: 9, Issue: 3, JulySeptember 2021" and orally presented at ARITH 2021.

A novel architecture of an all-digital transmitter is proposed in this paper, introducing stochastic computation to a single-bit polar topology. The proposed architecture exploits the benefits of stochastic computing to simplify the design of an all-digital transmitter and minimize hardware complexity. Complexity reduction is achieved by implementing a digital oscillator as a cosine function in the stochastic domain instead of resorting to LUT-based or CORDIC-based implementations. An evaluation of the introduced all-digital polar architecture shows that the power spectral density of the transmitted passband signal is similar to that of a conventional transmitter. Synthesis of the proposed stochastic-enabled transmitter at a 28-nm FDSOI technology node reveals its minimal complexity requirements and 87.13% area reduction compared to conventional implementations.

This paper introduces a delay modeling formulation for several Parallel-Prefix Adders in the presence of threshold voltage variability. A path-based model is derived for the delay variability of Kogge-Stone, Knowles, Sklansky, Brent-Kung, Han-Carlson, Ladner-Fischer, and New Adder architectures. The delay model accuracy is evaluated for the specific adders on the basis of SPICE Monte-Carlo Simulations at 45 nm and 16 nm nodes. The presented analysis reveals that the proposed path-based model estimates the maximum delay Probability Density Function of the particular adder architectures with sufficient accuracy, assuming 3σ intra-die threshold voltage variations as high as 10% of nominal value. Delay yield estimations produced by the proposed model are found to agree with those of Monte-Carlo Simulations for a number of highly probable critical paths, presenting an error less than 2%. For the particular adders and technology nodes, an approximately 10-fold reduction in simulation time is obtained when exploiting the proposed model. The particular observation indicates that the computational time for delay yield estimation of Parallel-Prefix Adders can be exponentially reduced with negligible accuracy loss when the analysis focuses solely on the Nominal-Maximum Delay critical path. Finally, a quantitative comparison of prefix adders to the Borrow-Save Adder is offered, in terms of complexity and susceptibility to variations.

Stochastic computing introduces massive parallelism in several practical applications by utilizing minimal-complexity processing elements, and provides inherent fault-tolerant features. However stochastic computation systems require long bit streams to achieve sufficient performance in terms of Signal to Noise Ratio. This paper proposes a first- and a second-order Noise-Shaping Binary-to-Stochastic Converter (NSBSC) for bipolar format. The proposed architecture schemes are compared with a baseline Binary-to-Stochastic Converter (BSC) in terms of Signal-to-Quantization-Noise Ratio (SQNR). It is shown that for certain test cases, the proposed architecture leads to 15.276 dB improved SQNR for the same bit stream length and, furthermore, achieves the same SQNR as the conventional converter using as much as 93.75% shorter stream lengths. Furthermore, the analysis includes area and power figures for the introduced hardware architectures for a 28-nm FDSOI technology. Finally, achieved NSBSC gains are shown to propagate at the output of a stochastic FIR filter, proving that the stochastic properties of the derived stream are maintained.

In this paper we investigate the impact of intra- and inter-die variations on the delay sensitivity of certain Residue Number System (RNS) arithmetic circuits in comparison to ordinary binary arithmetic logic. The timing yield of systems that contain multiply-add units (MAC) is of great importance since they dominate important applications such as digital signal processing. Specifically, we employ two different delay models for the estimation of delay distributions of RNS and binary MAC architectures. Our analysis quantitatively proves that RNS MAC architectures that use bases of the form {2n- 1, 2n, 2n+ 1} demonstrate better normalized delay variation than binary MAC architectures to characterize both their static timing behaviour and the timing behaviour taking into account the sensitizable paths. Furthermore, it is shown that certain simplified RNS MAC architectures outperform conventional RNS MAC architectures in terms of the μ + α · σ delay variation metric.