This live demonstration shows a frame-based CMOS vision sensor with high dynamic range for event generation. Our CMOS vision sensor features 64 × 64 processing elements that comprise one 4T-APS and local circuitry to provide events and high dynamic range extension. The event generation is performed synchronously through the threshold of the frame difference between consecutive frames. The dynamic range extension is carried out per-pixel with the overflow capacitance method. The sensor can reach up to thousands of event frames per second. Electrical simulations indicate a dynamic range of 85 dB, which narrows the gap with dynamic vision sensors.

This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.

This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown.

Neural network mixed-mode hardware accelerators for deep convolutional neural networks (CNN) strive to cope with a high number of input feature maps and increasing bit depths for both weights and inputs. As an example of this need, the ResNet model for image classification comprises 512 3× 3 feature filters in its conv5 layer. This would lead to 4068 multipliers driving a summing node for actual concurrent processing of all the input feature maps, which makes up a challenge in mixed-mode. This paper addresses the design of a 5-bit signed SRAM-based in-memory computing cell in 180 nm 3.3 V CMOS technology, dealing with the impact of increasing the number of input feature maps. The data presented in the paper are based on electrical and post layout simulations.

Indirect time of flight (IToF) allows for accurately retrieving 3D geometry without the need for exorbitant time resolution. Nevertheless, the use of continuous-wave (CW) periodic modulation brings the need for multiple frequency measurements to solve depth ambiguities or cope with multi-path interference. Sequential acquisition of multiple frames reduces the frame rate, while harmonic distortion of the modulation waveforms produces wiggling in the depth estimation. This paper presents and verifies the operation of an IToF CMOS image sensor designed to provide single-shot multi-frequency measurements. A macro-pixel structure allows acquiring multi-frame data in one shot, while resonant demodulation annihilates the harmonic content. The novel architecture consists of 10 $\mu m \times 10 \mu m$ 2 -tap pixels with a 20% fill factor (FF). Post-layout simulations show promising 3D reconstruction for up to 16 different simultaneous frequencies.

Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24×56 pixel proof-of-concept 0.18 μm standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 μW/pixel at 60 fps and a pixel pitch of 47 μm in a four pixels per processing element configuration.

Neuromorphic systems provide an alternative to conventional computing hardware, promising low-power operation suitable for sensory-processing and edge computing. In this paper, we present a mixed-signal processing system designed to provide on-sensor classification of signals obtained from multi-electrode array neural recordings. The designed circuits implement a real-time spike sorting algorithm, and operate on signals represented by asynchronous event streams. We combine analog circuits computation primitives (temporal surface generation, distance computation, winner-take-all) to implement a spatio-temporal clustering algorithm, classifying signals acquired by neighbouring electrodes. The prototype chip has been submitted for fabrication in a 180nm CMOS technology. The circuits are designed to fit, alongside signal conditioning and conversion circuits, in the area under the recording electrodes (below 80×80um per electrode). Circuit implementation details and simulation results are presented. The expected neural spike recognition rates of 75% in a single-layer network and 88% in a 2-layer network are comparable with a software implementation, while the system is designed to provide a low-power embedded real-time solution. This work provides a foundation towards the design of a large scale neuromorphic processing system, to be embedded in brain-machine interfaces.

Multiple object visual tracking of real time detected objects using a low-power embedded solution is shown. The proposal is implemented on a NVIDIA Jetson TX2 development kit demonstrating the feasibility of deep learning techniques for IoT and mobile edge computing applications.

Compute and memory demands of state-of-the-art deep learning methods are still a shortcoming that must be addressed to make them useful at Internet of Things (IoT) end-nodes. In particular, recent results depict a hopeful prospect for image processing using convolutional neural networks, CNNs, but the gap between software and hardware implementations is already considerable for IoT and mobile edge computing applications due to their high power consumption. This proposal performs low-power and real time deep learning-based multiple object visual tracking implemented on an NVIDIA Jetson TX2 development kit. It includes a camera and wireless connection capability and it is battery powered for mobile and outdoor applications. A collection of representative sequences captured with the on-board camera, dETRUSC video dataset, is used to exemplify the performance of the proposed algorithm and to facilitate benchmarking. The results in terms of power consumption and frame rate demonstrate the feasibility of deep learning algorithms on embedded platforms although more effort in the joint algorithm and hardware design of CNNs is needed.

Foreground segmentation algorithms are sometimes provided with feedback mechanisms to deal with complex scenarios such as dynamic backgrounds. This is accomplished with background dynamic estimators in the case of foreground detectors based on non-parametric models with a historical record of the background. This work introduces the Shannon entropy as a new background dynamics estimator. The paper shows that this approach leads to better figures of merit than those provided by the original background dynamics estimators in state-of-the-art algorithms such as PBAS and SuBSENSE for complex scenarios as dynamic backgrounds or camera jitter in the database ChangeDetection. Also, the Shannon entropy permits to decrease the number of samples in the background model, cutting memory usage, and thus making implementations on embedded devices easier.

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.

This live demonstration is related to ISCAS track “Sensory Systems: Sensor Networks”. This live demo shows a wireless sensor network of custom-made differential capacitive sensors with the ZigBee protocol for snail pest detection. The wireless sensor network provides the snail occupation level of a given plantation area. Validation of the wireless sensor network in both controlled mini plots in a greenhouse and outdoor small areas has been made.