Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires effective self-interference (SI) cancellers. RF SI cancellation (SIC) via frequency-domain equalization (FDE), where bandpass filters channelize the SI, is suited for integrated circuits (ICs). In this paper, we explore the limits and higher layer challenges associated with using such cancellers. We evaluate the performance of a custom FDE-based canceller using two testbeds; one with mobile FD radios and the other with upgraded, static FD radios in the PAWR COSMOS testbed. The latter is a lasting artifact for the research community, alongside a dataset containing baseband waveforms captured on the COSMOS FD radios, facilitating FD-related experimentation at the higher networking layers. We evaluate the performance of the FDE-based FD radios in both testbeds, with experiments showing 95 dB overall achieved SIC (52 dB from RF SIC) across 20 MHz bandwidth. We conduct network-level experiments for (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users, showing FD gains of$1.14\times $–$1.25\times $and$1.25\times $–$1.73\times $, respectively, confirming analytical results. We also evaluate the performance of an FD jammer-receiver, demonstrating a strong dependence on relative transmit power levels and modulation schemes.

Full-duplex (FD) wireless and phased arrays are both promising techniques that can significantly improve data rates in future wireless networks. However, integrating FD with transmit (Tx) and receive (Rx) phased arrays is extremely challenging, due to the large number of self-interference (SI) channels. Previous work relies on either RF canceller hardware or on analog/digital Tx beamforming (TxBF) to achieve SI cancellation (SIC). However, Rx beamforming (RxBF) and the data rate gain introduced by FD nodes employing beamforming have not been considered yet. We study FD phased arrays with joint TxBF and RxBF with the objective of achieving improved FD data rates. The key idea is to carefully select the TxBF and RxBF weights to achieve wideband RF SIC in the spatial domain with minimal TxBF and RxBF gain losses. Essentially, TxBF and RxBF are repurposed, thereby not requiring specialized RF canceller circuitry. We formulate the corresponding optimization problem and develop an iterative algorithm to obtain an approximate solution with provable performance guarantees. Using SI channel measurements and datasets, we extensively evaluate the performance of the proposed approach in different use cases under various network settings. The results show that an FD phased array with 9/36/72 elements can cancel the total SI power to below the noise floor with sum TxBF and RxBF gain losses of 10.6/7.2/6.9dB, even at Tx power level of 30dBm. Moreover, the corresponding FD rate gains are at least 1.33/1.66/1.68 ×.

To support experimentation with full-duplex (FD) wireless, we recently integrated two FlexICoN Gen-2 wideband FD radios in the open-access, city-scale NSF PAWR COSMOS testbed. Each integrated FD radio consists of an antenna, a customized Gen-2 RF self-interference (SI) canceller box, a USRP software-defined radio, and a remotely accessible compute node. The RF SI canceller box includes an RF canceller printed circuit board which emulates an integrated circuit implementation based on the technique of frequency-domain equalization. The Gen-2 canceller box can achieve up to 50 dB RF SI cancellation across 20MHz bandwidth. In this demo, we present the design and implementation of the open-acccess, remotely accessible FD radios that are integrated in the indoor COSMOS Sandbox 2 at Columbia University. We also demonstrate example experiments that are available to researchers, where demo participants can observe the visualized performance of the open-access FD radios.

In order to support experimentation with full-duplex (FD) wireless, we integrated the FlexICoN Gen-2 wideband FD radio with the city-scale PAWR COSMOS testbed [1]. In particular, the implemented FD radio consists of an antenna, a customized Gen-2 RF self-interference (SI) canceller box, a USRP software-defined radio (SDR), and a compute node. The RF canceller box includes an RF SI canceller implemented using discrete components on a printed circuit board (PCB), which emulates its RFIC canceller counterpart. The Gen-2 RF SI canceller achieves 50dB RF SI cancellation across 20MHz bandwidth using the technique of frequency-domain equalization (FDE) [2]. In this abstract, we present the design and implementation of the remotely accessible Gen-2 wideband FD radio integrated with the COSMOS sandbox at Columbia University. We also present an example real-time wideband FD wireless link demonstration using the GNU Radio software.

Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where reconfigurable RF filters are used to channelize the SI signal path. In [2], we designed and implemented an FDE-based RF canceller on a printed circuit board (PCB). We also presented an optimized canceller configuration scheme based on the derived canceller model, and extensively evaluated the performance of the FDE-based FD radios in a software-defined radio (SDR) testbed in different network settings.

Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where RF filters channelize the SI signal path. Unlike other FD implementations, that mostly rely on delay lines, FDE-based cancellers can be realized in small-form-factor devices. However, the fundamental limits and higher layer challenges associated with these cancellers were not explored yet. Therefore, and in order to support the integration with a software-defined radio (SDR) and to facilitate experimentation in a testbed with several nodes, we design and implement an FDE-based RF canceller on a printed circuit board (PCB). We derive and experimentally validate the PCB canceller model and present a canceller configuration scheme based on an optimization problem. We then extensively evaluate the performance of the FDE-based FD radio in the SDR testbed. Experiments show that it achieves 95dB overall SIC (52dB from RF SIC) across 20MHz bandwidth, and an average link-level FD gain of 1.87x. We also conduct experiments in: (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users. The experimental FD gains in the two types of networks confirm previous analytical results. They depend on the users' SNR values and the number of FD users, and are 1.14x-1.25x and 1.25x-1.73x, respectively. Finally, we numerically evaluate and compare the RFIC and PCB implementations and study various design tradeoffs.

Full-duplex (FD) wireless and phased arrays are both promising techniques that can significantly improve data rates in future wireless networks. However, integrating FD with transmit (Tx) and receive (Rx) phased arrays is extremely challenging, due to the large number of self-interference (SI) channels. Previous work relies on either RF canceller hardware or on analog/digital Tx beamforming (TxBF) to achieve SI cancellation (SIC). However, Rx beamforming (RxBF) and the data rate gain introduced by FD nodes employing beamforming have not been considered yet. We study FD phased arrays with joint TxBF and RxBF with the objective of achieving improved FD data rates. The key idea is to carefully select the TxBF and RxBF weights to achieve wideband RF SIC in the spatial domain with minimal TxBF and RxBF gain losses. Essentially, TxBF and RxBF are repurposed, thereby not requiring specialized RF canceller circuitry. We formulate the corresponding optimization problem and develop an iterative algorithm to obtain an approximate solution with provable performance guarantees. Using SI channel measurements and datasets, we extensively evaluate the performance of the proposed approach in different use cases under various network settings. The results show that an FD phased array with 9/36/72 elements can cancel the total SI power to below the noise floor with sum TxBF and RxBF gain losses of 10.6/7.2/6.9 dB, even at Tx power level of 30 dBm. Moreover, the corresponding FD rate gains are at least 1.33/1.66/1.68X.

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μm CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power consumption of the comparator trades with the speed which is simply controlled by the delay of the second stage. As a result, a low-power comparator for given offset and speed requirements can be designed efficiently.