Efficient resource allocation in cloud computing environments is crucial for ensuring platform performance and service quality. To address the heterogeneity of cloud resources and the diverse demands of cloud users, this paper proposes a truthful multi-combinatorial double auction (TMCDA) mechanism for cloud resource allocation. The mechanism introduces resource weight ratios to reflect the relative importance and proportional relationships among different resource types, thereby enabling a more precise evaluation of heterogeneous resource combinations. Meanwhile, cloud users are allowed to submit multiple substitutable combinatorial resource requests, which increases allocation flexibility and improves transaction success rates. In the payment design, a critical price calculation method similar to the second-price auction is adopted to guarantee truthfulness and economic efficiency. By integrating resource bundle matching with weighted pricing, the proposed mechanism improves resource utilization and overall social welfare. Simulation results demonstrate that, compared with Truthful Combinatorial/Multi-unit multi-item Double Auction for Cloud computing (TCMDAC) and Combinatorial Double Auction Resource Allocation (CDARA), the proposed approach achieves at least 15% and 30% improvements in social welfare, respectively, highlighting its advantages in transaction fairness, incentive compatibility, and allocation efficiency.

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6-μs automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

Physical unclonable function (PUF) is an important security primitive, which generates unique signatures as fingerprints for each chip. This article first presents a novel interconnect-based PUF (iPUF). The proposed iPUF utilizes the manufacturing process variability of interconnect lines to introduce crosstalk variations for generating PUF signatures. By leveraging the variations of passive interconnects, iPUF minimizes the usage of active CMOS components, providing an increased resiliency against environmental variations and aging. Initiated by a linear feedback shift register (LFSR), iPUF sequentially generates 1-bit signature at each clock cycle, making it more efficient compared with ring-oscillator PUF. Second, two schemes for signature uniqueness enhancement of sequential PUFs are proposed. The self-masking scheme windows the sequential signature with an m-bit mask trained by the PUF's own initial sequential signature. Meanwhile, the bit-filtering scheme screens the randomness of each bit within the sequential signature by exploiting several sub-iPUFs and selects the bits with high randomness. To verify the performance of iPUF, Monte Carlo simulations of 500 samples, with variations following industrial data, are conducted in different operating corners. The uniqueness of the given sample set approaches 48.63% with a 10-bit mask. With ±10% supply voltage, 0 °C-100 °C temperature variations, as well as one year of unaccelerated aging, iPUF's reliability values, are as high as 96.09%, 99.06%, and 99.63%, respectively. For verification, 50 dies of iPUF chips are manufactured with a 55-nm technology node. Silicon results demonstrate that iPUF generates 1024-bit signatures with satisfied uniqueness (48.03%) while exhibiting good reliability (90.07%) under 120-mV voltage variations. Finally, iPUF's robustness against various attacks is also proven.

With technology approaching to 14nm and below, the shrinking gate size makes IC reliability become a big concern. As the speed of CMOS and FinFET is degraded by aging mechanisms including negative bias temperature instability (NBTI) and hot carrier injection (HCI). At the same time, significant process variations differ the aging degradation rate of each individual IC, which cause significant failure time differences even for the ICs belonging to the same lot. Therefore, to efficiently bin the devices into the reliability tiers for different safety & security usages, it is necessary to perform predictive reliability screening during production test at time-zero. In this paper, a novel on-chip architecture for fast time-zero predictive aging screening (ZeroScreen) is proposed. The screening time is limited to 8.14ms per device considering 50MHz test clock frequency and 6.6 μs automatic test equipment (ATE) level settling time. In the experiment, 185 fresh FPGA devices under test (DUTs) implemented with ZeroScreen are binned into 4 predictive reliability bins by ZeroScreen. By comparing with the 8-hour accelerated burn-in results, the reliability screening errors of ZeroScreen are less than 6.5% and 4.3% for static and dynamic stress cases, respectively.

For 40nm and below technologies, billions of transistors can be integrated into a single chip. Meanwhile, the operation frequency has reached over Giga Hertz. In this case, highly synchronized switching activities can induce significant current, which leads to IR-drop. Excessive IR-drop can cause timing failure, abnormal reset, or disruption of data processing. As a result, dynamic voltage and frequency scaling (DVFS) system implemented effective adaptation strategies are widely used by SoCs to mitigate IR-Drop noise and stabilize performance. As the basis of DVFS action, economic and accurate IR-drop monitors are in great need. This paper presents a novel and efficient IR-Drop Alarmer, which can cooperate with the DVFS system for fast IR-drop adaptation. The IR-drop alarming threshold of the proposed sensor is configurable between 45mV to 120mV. Considering a 1.1ns width IR-drop noise, the IR noise sampling window can be as small as 0.125ns, with alarming duration error rate less than 6.8% for 97% of the Monte Carlo samples considering process variations. Furthermore, the proposed alarmer is composed by all-digital standard gates without an y high frequency sampling clock, which is of low area overhead and power consumption.