Jin Tack Lim

dblp:184/8223 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 2 first-authorSystems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Cloud and datacenter computing · 88% Processor architecture and microarchitecture · 12%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing
virtualization
1.032020
Optimizing Nested Virtualization Performance Using Direct Virtual Hardware · ASPLOS 2020
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
ARM Virtualization: Performance and Architectural Implications · ISCA 2016
Cloud and datacenter computing › virtualization
nested virtualization
0.722020
Optimizing Nested Virtualization Performance Using Direct Virtual Hardware · ASPLOS 2020
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
Cloud and datacenter computing › virtualization › virtualization performance
hypervisor performance
0.722020
Optimizing Nested Virtualization Performance Using Direct Virtual Hardware · ASPLOS 2020
ARM Virtualization: Performance and Architectural Implications · ISCA 2016
Processor architecture and microarchitecture › instruction set architecture › RISC
ARM architecture
0.422017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
ARM Virtualization: Performance and Architectural Implications · ISCA 2016
Cloud and datacenter computing › virtualization
virtual machine monitor
0.112017
NEVE: Nested Virtualization Extensions for ARM · SOSP 2017
Cloud and datacenter computing › virtualization
hardware-assisted virtualization
0.112016
ARM Virtualization: Performance and Architectural Implications · ISCA 2016

Methods — techniques the papers use, named apart from their topics

virtual timers · 0.4virtual passthrough · 0.4virtual inter-processor interrupts · 0.4direct virtual hardware · 0.4paravirtualization · 0.3measurement · 0.2
YearPublicationVenuePosition
2020 Optimizing Nested Virtualization Performance Using Direct Virtual Hardware
abstract
Nested virtualization, running virtual machines and hypervisors on top of other virtual machines and hypervisors, is increasingly important because of the need to deploy virtual machines running software stacks on top of virtualized cloud infrastructure. However, performance remains a key impediment to further adoption as application workloads can perform many times worse than native execution. To address this problem, we introduce DVH (Direct Virtual Hardware), a new approach that enables a host hypervisor, the hypervisor that runs directly on the hardware, to directly provide virtual hardware to nested virtual machines without the intervention of multiple levels of hypervisors. We introduce four DVH mechanisms, virtual-passthrough, virtual timers, virtual inter-processor interrupts, and virtual idle. DVH provides virtual hardware for these mechanisms that mimics the underlying hardware and in some cases adds new enhancements that leverage the flexibility of software without the need for matching physical hardware support. We have implemented DVH in the Linux KVM hypervisor. Our experimental results show that DVH can provide near native execution speeds and improve KVM performance by more than an order of magnitude on real application workloads.
Jin Tack Lim, Jason Nieh
ASPLOS1
2017 NEVE: Nested Virtualization Extensions for ARM
abstract
Nested virtualization, the ability to run a virtual machine inside another virtual machine, is increasingly important because of the need to deploy virtual machines running software stacks on top of virtualized cloud infrastructure. As ARM servers make inroads in cloud infrastructure deployments, supporting nested virtualization on ARM is a key requirement, which has been met recently with the introduction of nested virtualization support to the ARM architecture. We build the first hypervisor to use ARM nested virtualization support and show that despite similarities between ARM and x86 nested virtualization support, performance on ARM is much worse than on x86. This is due to excessive traps to the hypervisor caused by differences in non-nested virtualization support. To address this problem, we introduce a novel paravirtualization technique to rapidly prototype architectural changes for virtualization and evaluate their performance impact using existing hardware. Using this technique, we propose Nested Virtualization Extensions for ARM (NEVE), a set of simple architectural changes to ARM that can be used by software to coalesce and defer traps by logging the results of hypervisor instructions until the results are actually needed by the hypervisor or virtual machines. We show that NEVE allows hypervisors running real application workloads to provide an order of magnitude better performance than current ARM nested virtualization support and up to three times less overhead than x86 nested virtualization. NEVE will be included in ARMv8.4, the next version of the ARM architecture.
Jin Tack Lim, Christoffer Dall, Shih-Wei Li, Jason Nieh, Marc Zyngier
SOSP1
2016 ARM Virtualization: Performance and Architectural Implications
abstract
ARM servers are becoming increasingly common, making server technologies such as virtualization for ARM of growing importance. We present the first study of ARM virtualization performance on server hardware, including multi-core measurements of two popular ARM and x86 hypervisors, KVM and Xen. We show how ARM hardware support for virtualization can enable much faster transitions between VMs and the hypervisor, a key hypervisor operation. However, current hypervisor designs, including both Type 1 hypervisors such as Xen and Type 2 hypervisors such as KVM, are not able to leverage this performance benefit for real application workloads. We discuss the reasons why and show that other factors related to hypervisor software design and implementation have a larger role in overall performance. Based on our measurements, we discuss changes to ARM's hardware virtualization support that can potentially bridge the gap to bring its faster VM-to-hypervisor transition mechanism to modern Type 2 hypervisors running real applications. These changes have been incorporated into the latest ARM architecture.
Christoffer Dall, Shih-Wei Li, Jin Tack Lim, Jason Nieh, Georgios Koloventzos
ISCA3