Urban change detection (CD) is crucial for informed decision-making but faces various challenges, including complex features, rapid changes, and extensive human interventions. These challenges underscore the urgent need for innovative multiclass CD (MCD) techniques that extensively incorporate deep learning (DL). Despite several successes achieved with the DL-based MCD methods, still certain shortcomings persist, including the disregard for spatial principles, which significantly hinders the seamless integration of geoscience-knowledge and artificial-intelligence. In this article, a novel DL model known as the position-aware graph-convolutional neural network (CNN) fusion network (PGCFN) is introduced, integrating spatial position encoding to effectively detect urban changes. The model’s first part encodes geospatial positions following Tobler’s first law (TFL) of geography. It then integrates encoded positions into an MCD model, combining a graph attention network (GAT) with a CNN to enhance performance. The model was tested on 0.5-m resolution remote sensing (RS) images, achieving an impressive minimum mean intersection over union (MIoU) score of 91.20%. Additionally, the model’s position-aware graph attention module exhibited a strong emphasis on geographic proximity when evaluating connections between superpixels. Overall, these findings affirm that our model could effectively addresses urban CD challenges and significantly enhances the integration of geoscience knowledge and artificial intelligence (AI).

Digital systems storing cadastral data in vector format are considered effective due to their ability of offering interactive services to citizens and other land-related systems. The adoption of such systems is ubiquitous, but when adopted, they create two non-compatible systems with paper-based cadastral systems whose information needs to be digitised. This study proposes a new approach that is fast and accurate for transforming paper-based cadastral data into digital systems. The proposed method involves deep-learning techniques of the LCNN and ResNet-50 for detecting cadastral parcels and their numbers, respectively, from the cadastral plans. It also contains four functions defined to speed up transformations and compilations of the cadastral plan’s data in digital systems. The LCNN is trained and validated with 968 samples. The ResNet-50 is trained and validated with 106,000 samples. The Structural-Average-Precision (sAP10) achieved with the LCNN was 0.9057. The Precision, Recall and F1-Score achieved with the ResNet-50 were 0.9650, 0.9648 and 0.9649, respectively. These results confirmed that the new method is accurate enough for implementation, and we tested it with a huge set of data from Tanzania. Its performance from the experimented data shows that the proposed method could effectively transform paper-based cadastral data into digital systems.

Manycore processors, with tens to hundreds of tiny cores but no hardware-based cache coherence, can offer tremendous peak throughput on highly parallel programs while being complexity and energy efficient. Manycore processors can be combined with a few high-performance big cores for executing operating systems, legacy code, and serial regions. These systems use heterogeneous cache coherence (HCC) with hardware-based cache coherence between big cores and software-centric cache coherence between tiny cores. Unfortunately, programming these heterogeneous cache-coherent systems to enable collaborative execution is challenging, especially when considering dynamic task parallelism. This paper seeks to address this challenge using a combination of light-weight software and hardware techniques. We provide a detailed description of how to implement a work-stealing runtime to enable dynamic task parallelism on heterogeneous cache-coherent systems. We also propose direct task stealing (DTS), a new technique based on user-level interrupts to bypass the memory system and thus improve the performance and energy efficiency of work stealing. Our results demonstrate that executing dynamic task-parallel applications on a 64-core system (4 big, 60 tiny) with complexity-effective HCC and DTS can achieve: $7 \times$ speedup over a single big core; $1.4 \times$ speedup over an area-equivalent eight bigcore system with hardware-based cache coherence; and 21% better performance and similar energy efficiency compared to a 64-core system (4 big, 60 tiny) with full-system hardware-based cache coherence.

Task-based parallel programming frameworks offer compelling productivity and performance benefits for modern chip multi-processors (CMPs). At the same time, CMPs also provide packed-SIMD units to exploit fine-grain data parallelism. Two fundamental challenges make using packed-SIMD units with task-parallel programs particularly difficult: (1) the intra-core parallel abstraction gap; and (2) inefficient execution of irregular tasks. To address these challenges, we propose augmenting CMPs with intra-core loop-task accelerators (LTAs). We introduce a lightweight hint in the instruction set to elegantly encode loop-task execution and an LTA microarchitectural template that can be configured at design time for different amounts of spatial/temporal decoupling to efficiently execute both regular and irregular loop tasks. Compared to an in-order CMP baseline, CMP+LTA results in an average speedup of 4.2X (1.8X area normalized) and similar energy efficiency. Compared to an out-of-order CMP baseline, CMP+LTA results in an average speedup of 2.3X (1.5X area normalized) and also improves energy efficiency by 3.2X. Our work suggests augmenting CMPs with lightweight LTAs can improve performance and efficiency on both regular and irregular loop-task parallel programs with minimal software changes.

This poster will describe a taped-out 2×2mm 1.3 M-transistor test chip in IBM 130 nm designed using our new Python-based hardware modeling framework. The goal of our tapeout was to demonstrate the ability of this framework to enable Agile hardware design flows.

Amdahl's law provides architects a compelling reason to introduce system asymmetry to optimize for both serial and parallel regions of execution. Asymmetry in a multicore processor can arise statically (e.g., from core microarchitecture) or dynamically (e.g., applying dynamic voltage/frequency scaling). Work stealing is an increasingly popular approach to task distribution that elegantly balances task-based parallelism across multiple worker threads. In this paper, we propose asymmetry-aware work-stealing (AAWS) runtimes, which are carefully designed to exploit both the static and dynamic asymmetry in modern systems. AAWS runtimes use three key hardware/software techniques: work-pacing, work-sprinting, and work-mugging. Work-pacing and work-sprinting are novel techniques that combine a marginal-utility-based approach with integrated voltage regulators to improve performance and energy efficiency in high-and low-parallel regions. Work-mugging is a previously proposed technique that enables a waiting big core to preemptively migrate work from a busy little core. We propose a simple implementation of work-mugging based on lightweight user-level interrupts. We use a vertically integrated research methodology spanning software, architecture, and VLSI to make the case that holistically combining static asymmetry, dynamic asymmetry, and work-stealing runtimes can improve both performance and energy efficiency in future multicore systems.