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Moein Khazraee

dblp:184/8325 · DBLP profile ↗
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8ranked-venue papers
4as first author
3since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 1 since 2021Computer networks · 4 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 3 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
5 papers
Software-defined and programmable networks · 31% Wireless networking · 25% Physical-layer communications · 23%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Hardware accelerators and domain-specific architectures · 25% Reconfigurable computing and FPGAs · 19% Distributed systems · 19%

Topics — the 13 heaviest of 21, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Physical-layer communications
software-defined radio
1.022022
Observing wideband RF spectrum with low-cost, resource limited SDRs · MobiSys 2022
SparSDR: Sparsity-proportional Backhaul and Compute for SDRs · MobiSys 2019
Network optimization and economics › network design
network topology design
0.712023
TopoOpt: Co-optimizing Network Topology and Parallelization Strategy for Distributed Training Jobs · NSDI 2023
Software-defined and programmable networks › programmable data plane
packet processing pipeline
0.712023
Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant · ASPLOS (3) 2023
Software-defined and programmable networks
programmable data plane
0.712023
Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant · ASPLOS (3) 2023
Distributed systems › distributed machine learning
distributed training
0.712023
TopoOpt: Co-optimizing Network Topology and Parallelization Strategy for Distributed Training Jobs · NSDI 2023
Electronic design automation › design optimization
topology optimization
0.712023
TopoOpt: Co-optimizing Network Topology and Parallelization Strategy for Distributed Training Jobs · NSDI 2023
Wireless networking › cognitive radio
spectrum sensing
0.622022
SweepSense: Sensing 5 GHz in 5 Milliseconds with Low-cost Radios · NSDI 2019
Observing wideband RF spectrum with low-cost, resource limited SDRs · MobiSys 2022
Hardware accelerators and domain-specific architectures › domain-specific accelerator
ASIC accelerator
0.522017
Moonwalk: NRE Optimization in ASIC Clouds · ASPLOS 2017
ASIC Clouds: Specializing the Datacenter · ISCA 2016
Wireless networking › cognitive radio › spectrum sensing
wideband spectrum sensing
0.412019
SweepSense: Sensing 5 GHz in 5 Milliseconds with Low-cost Radios · NSDI 2019
Cloud and datacenter computing
datacenter architecture
0.212016
ASIC Clouds: Specializing the Datacenter · ISCA 2016
Hardware accelerators and domain-specific architectures
hardware-software interface
0.212023
Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant · ASPLOS (3) 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator
0.112016
ASIC Clouds: Specializing the Datacenter · ISCA 2016
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator
0.112016
ASIC Clouds: Specializing the Datacenter · ISCA 2016

Methods — techniques the papers use, named apart from their topics

standardized interface · 1.3hardware/software decoupling · 1.3pareto-optimal design · 0.5computational fluid dynamics · 0.5sparse sampling · 0.4signal reconstruction · 0.4NRE optimization · 0.3place-and-route · 0.2place and route · 0.2
YearPublicationVenuePosition
2023 Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant
abstract
We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ∼200 ‍Gbps of traffic while adding only 0.7–7 microseconds of latency.
Moein Khazraee, Alex Forencich, George Papen, Alex C. Snoeren, Aaron Schulman
ASPLOS (3)1
2023 TopoOpt: Co-optimizing Network Topology and Parallelization Strategy for Distributed Training Jobs
Weiyang Wang, Moein Khazraee, Zhizhen Zhong, Manya Ghobadi, Dheevatsa Mudigere, Ying Zhang 0022, Anthony Kewitsch
NSDI2
2022 Observing wideband RF spectrum with low-cost, resource limited SDRs
abstract
Software Defined Radios (SDRs) combine a universal radio frontend with flexible processing. The radio frontend can be tuned to capture various wireless signals, while software processing allows quick and scalable deployment for diverse applications. SDRs seem like a good fit for the ever-evolving needs of today's spectrum usage: SDRs can be deployed today, then managed and upgraded with software to support the needs of tomorrow. However, the prevailing architecture of SDRs prevent real-time observation of wideband RF signals due to backhaul and processing resource constraints.
Raghav Subbaraman, Nishant Bhaskar, Sam Crow, Moein Khazraee, Aaron Schulman, Dinesh Bharadia
MobiSys4
2019 SparSDR: Sparsity-proportional Backhaul and Compute for SDRs
abstract
We present SparSDR, a resource-efficient architecture for softwaredefined radios whose backhaul bandwidth and compute power requirements scale in inverse proportion to the sparsity (in time and frequency) of the signals received. SparSDR requires dramatically fewer resources than existing approaches to process many popular protocols while retaining both flexibility and fidelity. We demonstrate that our approach has negligible impact on signal quality, receiver sensitivity, and processing latency. The SparSDR architecture makes it possible to capture signals across bandwidths far wider than the capacity of a radio's backhaul through the addition of lightweight frontend processing and corresponding backend reconstruction to restore the signals to their original sample rate. We employ SparSDR to develop two wideband applications running on a USRP N210 and a Raspberry Pi 3+: an IoT sniffer that scans 100 MHz of bandwidth and decodes received BLE packets, and a wideband Cloud SDR receiver that requires only residential-class Internet uplink capacity. We show that our SparSDR implementation fits in the constrained resources of popular low-cost SDR platforms, such as the AD Pluto.
Moein Khazraee, Yeswanth Guddeti, Sam Crow, Alex C. Snoeren, Kirill Levchenko, Dinesh Bharadia, Aaron Schulman
MobiSys1
2019 SweepSense: Sensing 5 GHz in 5 Milliseconds with Low-cost Radios
Yeswanth Guddeti, Raghav Subbaraman, Moein Khazraee, Aaron Schulman, Dinesh Bharadia
NSDI3
2017 Moonwalk: NRE Optimization in ASIC Clouds
abstract
Cloud services are becoming increasingly globalized and data-center workloads are expanding exponentially. GPU and FPGA-based clouds have illustrated improvements in power and performance by accelerating compute-intensive workloads. ASIC-based clouds are a promising way to optimize the Total Cost of Ownership (TCO) of a given datacenter computation (e.g. YouTube transcoding) by reducing both energy consumption and marginal computation cost.
Moein Khazraee, Luis Vega, Michael B. Taylor
ASPLOS1
2016 ASIC Clouds: Specializing the Datacenter
abstract
GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ownership (TCO) of large, high-volume chronic computations, which are becoming increasingly common as more and more services are built around the Cloud model. On the surface, the creation of ASIC clouds may seem highlyimprobable due to high NREs and the inflexibility of ASICs. Surprisingly, however, large-scale ASIC Clouds have already been deployed by a large number of commercial entities, to implement the distributed Bitcoin cryptocurrency system. We begin with a case study of Bitcoin mining ASIC Clouds, which are perhaps the largest ASIC Clouds to date. From there, we design three more ASIC Clouds, including a YouTube-style video transcoding ASIC Cloud, a Litecoin ASIC Cloud, and a Convolutional Neural Network ASIC Cloud and show 2-3 orders of magnitude better TCO versus CPU and GPU. Among our contributions, we present a methodology that given an accelerator design, derives Pareto-optimal ASIC Cloud Servers, by extracting data from place-and-routed circuits and computational fluid dynamic simulations, and then employing clever but brute-force search to find the best jointly-optimized ASIC, DRAM subsystem, motherboard, power delivery system, cooling system, operating voltage, and case design. Moreover, we show how data center parameters determine which of the many Pareto-optimal points is TCO-optimal. Finally we examine when it makes sense to build an ASIC Cloud, and examine the impact of ASIC NRE.
Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez, Michael B. Taylor
ISCA2
2013 A novel hardware implementation for joint heart rate, respiration rate, and gait analysis applied to body area networks
abstract
Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small applicable sensors and wireless data communication. Gait analysis is essential for the precise ECG and respiration analysis according to the body posture. A new comprehensive high-speed six-state design is utilized to cover all walking habits. Moreover, the collected data is sent to an external device for further monitoring. The proposed framework is optimized for hardware implementation and targeted for low power applications. The optimized joint implementation of these health-related sensors makes the proposed design distinct from the previous work.
Moein Khazraee, Ali Reza Zamani, Mohammad Hallajian, Seyed Pooya Ehsani, Hadi Asghari Moghaddam, Alireza Parsafar, Mahdi Shabany
ISCAS1