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Roman Kaplan

dblp:185/0231 · DBLP profile ↗
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6ranked-venue papers
4as first author
2since 2021 · last 2024
0000-0003-3722-0739ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6 · 4 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 39% Storage systems · 30% Parallel and multicore computing · 30%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel architecture
associative processor
0.612022
GIRAF: General Purpose In-Storage Resistive Associative Framework · IEEE Trans. Parallel Distributed Syst. 2022
Storage systems › computational storage
in-storage computing
0.612022
GIRAF: General Purpose In-Storage Resistive Associative Framework · IEEE Trans. Parallel Distributed Syst. 2022
Memory systems
processing-in-memory
0.612022
GIRAF: General Purpose In-Storage Resistive Associative Framework · IEEE Trans. Parallel Distributed Syst. 2022

Methods — techniques the papers use, named apart from their topics

resistive CAM · 0.6in-data processing · 0.6
YearPublicationVenuePosition
2024 Intel Gaudi 3 AI Accelerator: Architected for Gen AI Training and Inference
abstract
•OAM: Open Compute Platform Acceleration Module •2 compute dies connected over an interposer bridge •8 HBM2e stacks •Up to 900W with air cooling •Up to 1200W with liquid cooling •PCIe Gen5×16 •24x 200GbE RoCE via 48 112G PAM4 Serdes
Roman Kaplan
HCS1
2022 GIRAF: General Purpose In-Storage Resistive Associative Framework
abstract
GIRAF is a General purpose In-storage Resistive Associative Framework based on resistive content addressable memory (RCAM), which functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing deep in-data, rather than near-data, processing. We show that GIRAF outperformed a reference computer architecture with a bandwidth-limited external storage access on a variety of data-intensive workloads. The performance of GIRAF Dot Product and Sparse Matrix-Vector multiplication exceeds the attainable performance of a reference architecture by 1200 × and 130 ×, respectively.
Leonid Yavits, Roman Kaplan, Ran Ginosar
IEEE Trans. Parallel Distributed Syst.2
2020 BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data
abstract
Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive.
Roman Kaplan, Leonid Yavits, Ran Ginosar
SYSTOR1
2019 POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data
abstract
Genome sequences contain hundreds of millions of DNA base pairs. Finding the degree of similarity between two genomes requires executing a compute-intensive dynamic programming algorithm, such as Smith-Waterman. Traditional von Neumann architectures have limited parallelism and cannot provide an efficient solution for large-scale genomic data. Approximate heuristic methods (e.g. BLAST) are commonly used. However, they are suboptimal and still compute-intensive. In this work, we present BioSEAL, a biological sequence alignment accelerator. BioSEAL is a massively parallel non-von Neumann processing-in-memory architecture for large-scale DNA and protein sequence alignment. BioSEAL is based on resistive content addressable memory, capable of energy-efficient and high-performance associative processing. We present an associative processing algorithm for entire database sequence alignment on BioSEAL and compare its performance and power consumption with state-of-art solutions. We show that BioSEAL can achieve up to 57x speedup and 156x better energy efficiency, compared with existing solutions for genome sequence alignment and protein sequence database search.
Roman Kaplan, Leonid Yavits, Ran Ginosar
PACT1
2019 POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework
abstract
GIRAF is an in-storage architecture and algorithm framework based on Resistive Content Addressable Memory (RCAM). GIRAF functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that GIRAF outperforms a reference computer architecture with a bandwidth-limited external storage access on a variety of data intensive workloads. The performance of GIRAF Euclidean distance, dot product and histogram implementation, exceeds the attainable performance of a reference architecture by up to four orders of magnitude, depending on the dataset size. The performance of GIRAF SpMV exceeds the attainable performance of such reference architecture by more than two orders of magnitude.
Leonid Yavits, Roman Kaplan, Ran Ginosar
PACT2
2016 Student Research Poster: From Processing-in-Memory to Processing-in-Storage
abstract
In Most contemporary high performance computers are based on von Neumann architecture. It is widely recognized that such architecture suffers from CPU-memory bottleneck. The problem affects both performance and power efficiency of multicore and manycore architectures. With continuation of CPU scaling (driven by Moore's law and parallelization), the von Neumann bottleneck problem will become even more acute. Another major factor affecting today's high performance computing is the slowdown in scaling of traditional charge-based memories such as DRAM and NAND Flash. In response, many novel nano-devices and materials are under investigation to create an alternative to charge-based memory, namely resistive memory. Such alternatives include memristors, RRAM, PCM, 3D Xpoint, STT-MRAM and others. These technologies have a wide range of potential applications beyond memory, including solid state disks, digital computing, neuromorphic computing, etc. New approaches for processing-in-memory (PiM) have been suggested. One promising technology is 3D stacking, which integrates separate logic and DRAM layers with high-bandwidth, low-energy through-silicon vias. Leveraging 3D stacking technology, researchers have proposed near-DRAM acceleration architectures that integrate accelerator logic and custom 3D DRAM devices. They focus on either accelerator architecture, where the memory system is separate from the host processor's main memory system or the integration of accelerators and DRAM
Roman Kaplan
PACT1