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Moohyeon Nam

dblp:186/1049 · DBLP profile ↗
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5ranked-venue papers
2as first author
1since 2021 · last 2026
0009-0009-7004-7094ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Storage systems · 42% Memory systems · 22% Hardware accelerators and domain-specific architectures · 18%
Databases, data mining, and information retrieval
1 paper
Information retrieval · 100%

Topics — the 13 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
approximate nearest neighbor search
1.012026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Processor architecture and microarchitecture › computer arithmetic › floating-point arithmetic
mixed-precision arithmetic
1.012026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Hardware accelerators and domain-specific architectures › domain-specific accelerator
vector search accelerator
1.012026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Storage systems › indexing
b-tree
0.412020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020
Storage systems › transaction support › transactional storage
failure atomicity
0.412020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020
Storage systems › indexing
index structure
0.412020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020
Memory systems › non-volatile memory › persistent memory
persistent memory indexing
0.412020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020
Memory systems › non-volatile memory
persistent memory
0.412019
Write-Optimized Dynamic Hashing for Persistent Memory · FAST 2019
Information retrieval › similarity search › nearest neighbor search › approximate nearest neighbor search
graph-based ANNS
0.312026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Information retrieval
retrieval-augmented generation
0.312026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Information retrieval
similarity search
0.312026
Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering · IEEE Trans. Computers 2026
Memory systems
non-volatile memory
0.222020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020
Write-Optimized Dynamic Hashing for Persistent Memory · FAST 2019
Memory systems › non-volatile memory › persistent memory
byte-addressable persistent memory
0.112020
B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory · ACM Trans. Storage 2020

Methods — techniques the papers use, named apart from their topics

SIMD · 2.0HNSW · 2.0ASIC design · 2.0cacheline flush reduction · 0.48-byte store instructions · 0.4
YearPublicationVenuePosition
2026 Q-VESA: Accelerating Quantization-Aware Vector Search for Fast Retrieval in Prompt Engineering
abstract
Similarity search has drawn significant attention due to the growing demand for AI prompt engineering, which leverages retrieval-augmented generation (RAG) systems to maximize the efficiency of large language models (LLMs). Improving the performance of memory-intensive data retrieval processes using approximate nearest neighbor search (ANNS) algorithms has become increasingly crucial for delivering high-quality generative AI services.In this work, we propose Q-VESA, a software-hardware collaborative solution designed to accelerate low-precision graph-based vector search while preserving recall rates comparable to high-precision. We perform a comprehensive analysis of hierarchical navigable small-world (HNSW), one of the most promising graph-based ANNS methods, using recent datasets tailored for RAG systems. Unlike standard vector database datasets, vector data used in LLMs present unique challenges for low-precision search. To address these, we introduce software-oriented precision partitioning techniques that enable mixed-precision computations during graph traversal without compromising hardware performance. The Q-VESA architecture is developed with two key innovations: a database restructuring scheme with vector data segments, and a dedicated accelerator design to maximize throughput in distance computations. Experimental results demonstrate that Q-VESA on a CPU system achieves query-per-second (QPS) speedups of up to 1.81× in the SIMD execution mode. Furthermore, leveraging minimal area overhead, the ASIC implementation delivers an additional speedup of up to 58.3×, 16.5× and 1.5× compared to the CPU, GPU and the state-of-the-art ASIC-based accelerator, respectively.
Seongjoon Cho, Moohyeon Nam, Hongchan Roh, Moo-Kyoung Chung, Se-Hyun Yang, Seungkyu Choi
IEEE Trans. Computers4
2020 B3-Tree: Byte-Addressable Binary B-Tree for Persistent Memory
abstract
In this work, we propose B 3 -tree , a hybrid index for persistent memory that leverages the byte-addressability of the in-memory index and the page locality of B-trees. As in the byte-addressable in-memory index, B 3 -tree is updated by 8-byte store instructions. Also, as in disk-based index, B 3 -tree is failure-atomic since it makes every 8-byte store instruction transform a consistent index into another consistent index without the help of expensive logging. Since expensive logging becomes unnecessary, the number of cacheline flush instructions required for B 3 -tree is significantly reduced. Our performance study shows that B 3 -tree outperforms other state-of-the-art persistent indexes in terms of insert and delete performance. While B 3 -tree shows slightly worse performance for point query performance, the range query performance of B 3 -tree is 2x faster than FAST and FAIR B-tree because the leaf page size of B 3 -tree can be set to 8x larger than that of FAST and FAIR B-tree without degrading insertion performance. We also show that read transactions can access B 3 -tree without acquiring a shared lock because B 3 -tree remains always consistent while a sequence of 8-byte write operations are making changes to it. As a result, B 3 -tree provides high concurrency level comparable to FAST and FAIR B-tree.
Hokeun Cha, Moohyeon Nam, Kibeom Jin, Jiwon Seo 0002, Beomseok Nam
ACM Trans. Storage2
2019 Write-Optimized Dynamic Hashing for Persistent Memory
Moohyeon Nam, Hokeun Cha, Young-ri Choi, Sam H. Noh, Beomseok Nam
FAST1
2017 EclipseMR: Distributed and Parallel Task Processing with Consistent Hashing
abstract
We present EclipseMR, a novel MapReduce framework prototype that efficiently utilizes a large distributed memory in cluster environments. EclipseMR consists of double-layered consistent hash rings - a decentralized DHT-based file system and an in-memory key-value store that employs consistent hashing. The in-memory key-value store in EclipseMR is designed not only to cache local data but also remote data as well so that globally popular data can be distributed across cluster servers and found by consistent hashing. In order to leverage large distributed memories and increase the cache hit ratio, we propose a locality-aware fair (LAF) job scheduler that works as the load balancer for the distributed in-memory caches. Based on hash keys, the LAF job scheduler predicts which servers have reusable data, and assigns tasks to the servers so that they can be reused. The LAF job scheduler makes its best efforts to strike a balance between data locality and load balance, which often conflict with each other. We evaluate EclipseMR by quantifying the performance effect of each component using several representative MapReduce applications and show EclipseMR is faster than Hadoop and Spark by a large margin for various applications.
Vicente A. B. Sanchez, Wonbae Kim, Youngmoon Eom, Kibeom Jin, Moohyeon Nam, Deukyeon Hwang, Jik-Soo Kim, Beomseok Nam
CLUSTER5
2016 Parallel Tree Traversal for Nearest Neighbor Query on the GPU
abstract
The similarity search problem is found in many application domains including computer graphics, information retrieval, statistics, computational biology, and scientific data processing just to name a few. Recently several studies have been performed to accelerate the k-nearest neighbor (kNN) queries using GPUs, but most of the works develop brute-force exhaustive scanning algorithms leveraging a large number of GPU cores and none of the prior works employ GPUs for an n-ary tree structured index. It is known that multi-dimensional hierarchical indexing trees such as R-trees are inherently not well suited for GPUs because of their irregular tree traversal and memory access patterns. Traversing hierarchical tree structures in an irregular manner makes it difficult to exploit parallelism since GPUs are tailored for deterministic memory accesses. In this work, we develop a data parallel tree traversal algorithm, Parallel Scan and Backtrack (PSB), for kNN query processing on the GPU, this algorithm traverses a multi-dimensional tree structured index while avoiding warp divergence problems. In order to take advantage of accessing contiguous memory blocks, the proposed PSB algorithm performs linear scanning of sibling leaf nodes, which increases the chance to optimize the parallel SIMD algorithm. We evaluate the performance of the PSB algorithm against the classic branch-and-bound kNN query processing algorithm. Our experiments with real datasets show that the PSB algorithm is faster by a large margin than the branch-and-bound algorithm.
Moohyeon Nam, Jinwoong Kim, Beomseok Nam
ICPP1