During the unprecedented expansion of global data, efficient storage solutions are essential for processing massive datasets stored on modern storage devices. B-epsilon-tree (Bε-tree) is one of the most well-known techniques that provides a write-optimized structure for database file systems. With the excellent access performance and high energy efficiency of solid-state drives (SSDs), they are expected to yield promising outcomes for large-scale data computation. However, their integration into storage systems has the challenges of write amplification, which impacts SSD endurance and reliability. This work identifies significant write amplification issues with Bε-tree implementations on SSDs due to the complicated management of key-value pairs. To mitigate the impact of write amplification, we propose PULSE, a novel scheme that rethinks Bε-tree designs by leveraging log-structured techniques optimized for SSDs. Moreover, PULSE integrates auxiliary indexing and a dual flush selector to minimize write amplification. Experimental results demonstrate that PULSE significantly mitigates write amplification by more than 62.6% on SSDs for the representative benchmarks compared to the Bε-tree.

In recent years, solid-state drives (SSDs) are gradually replacing traditional hard disk drives (HDDs) as the primary storage devices. It offers advantages such as shock resistance, higher speed, and a more compact size. As storage demands escalate, the concept of multi-level cells (MLC, TLC, QLC, etc.) has begun to emerge. While this approach increases capacity, it also introduces significant challenges: greater bits per cell lead to faster wear-out, longer read/write latency, and elevated energy consumption. To address these issues, the integration of various Gray codes into NAND flash memory encoding has shown promise. In this paper, we propose an Adaptive Gray code strategy (AdaGray), which leverages two distinct Gray code encoding schemes and dynamically allocates data into suitable coding blocks based on their characteristics. Experimental results demonstrate that AdaGray achieves a 24.31% reduction in write latency and lowers the erase count by up to 35.77%. More importantly, it significantly reduces the energy overhead from garbage collection by up to 45%, resulting in as much as 6982.8 mJ of energy savings.

3D NAND flash memory is one of the most important storage technologies in modern computer systems because of its non-volatile nature and excellent data access performance. However, it suffers from aging and reliability issues due to its inherent property. In contrast to the previous research that tried to recover the data with additional encoding techniques, we propose a novel reprogramming technique, called CellRejuvo, to improve the reliability of NAND flash cells. To the best of our knowledge, CellRejuvo is the pioneer for data recovery technique that cleverly leverages reprogramming to alleviate cell aging, extending the lifespan of solid-state drives. We implement CellRejuvo on a real 3D NAND flash-based SSD and evaluate its capability on various realistic workloads. The extensive experimental results show that CellRejuvo successfully reduces the error rate of SSD by an average of 38.28% under various retention times.

The increasing demand for high-quality graphics on mobile devices necessitates a high frame rate for display refresh. However, current process scheduling and memory management policies fail to consider the computation demands of frame rendering because they are optimized for saving energy and resource utilization. This leads to unresponsive displays for mobile users due to rendering delays. Accurately estimating computation demands is challenging for the mobile operating system, particularly under memory pressure, without display-specific semantics from user space. Moreover, the complexity of frame rendering makes it infeasible to schedule them with real-time policies. To address these issues, we propose a new framework called REFROM that utilizes a history-based frame time estimator to analyze frame time samples from UI threads and predict the computation requirements of upcoming frames. Experimental results demonstrate that REFROM reduces the number of delayed frames by up to 40% and improves up to 4% energy efficiency compared to the existing approaches.

Recently, phase-change memory (PCM) has emerged as a promising memory and storage technology. By storing multiple bits in a PCM cell, multi-level-cell (MLC) PCM further reduces the per-bit cost to improve its competitiveness. However, MLC PCM suffers from the high write latency and energy consumption caused by its complex write operations. Different from the existing works that attempt to improve the write latency and energy efficiency of the physical program & verify strategy for MLC PCM, we propose DTC, a drift-tolerant coding scheme, to apply fast write operation on MLC PCM without sacrificing the data accuracy. By exploiting the resistance drift and asymmetric write characteristics of PCM cells, the proposed DTC can significantly reduce the write latency and energy consumption of MLC PCM. Meanwhile, we propose a segmentation strategy to further improve the write performance with our coding scheme and an elimination methodology to avoid issuing unnecessary update operations. A series of analyses and experiments was conducted to evaluate the capability of the proposed scheme. It is encouraging that the proposed scheme can reduce 16.8%–32.1% energy consumption and 20.1%–32.6% write latency under the representative benchmarks, compared with the existing well-known schemes.

With the advent of the Internet of Things (IoT), more and more wearable devices have been developed and integrated into our daily lives. Energy efficiency is critical for these devices because they are typically run on energy-constrained resources like batteries or energy harvesters. The storage-class memory (SCM) technologies and data compression techniques could improve their energy efficiency via reducing data movements and squeezing the data size, respectively, where data compression is especially important for IoT and embedded systems to reduce the volume of data for the space-constrained memory/storage devices. Nevertheless, both of them cannot be aware of their inherent characteristics for further minimization of energy consumption. To this end, a write-friendly coding scheme is proposed in this work that jointly manages both techniques to yield energy-efficient SCM-based systems. Moreover, a novel design of ignorable bits is presented to partially skip write operations after completing data compression without sacrificing data accuracy. We evaluate the proposed scheme via a series of intensive experiments, the experimental results of which indicate that the proposed coding scheme reduces energy consumption by up to 45% under the investigated benchmarks.

Phase-Change Memory (PCM) has emerged as a promising memory and storage technology in recent years, and Multi-Level-Cell (MLC) PCM further reduces the per-bit cost to improve its competitiveness by storing multiple bits in each PCM cell. However, MLC PCM has high energy consumption issue in its write operations. In contrast to existing works that try to enhance the energy efficiency of the physical program&verify strategy for MLC PCM, this work proposes a drift-tolerant coding scheme to enable the fast write operation on MLC PCM without sacrificing any data accuracy. By exploiting the resistance drift and asymmetric write characteristic of PCM cells, the proposed scheme can reduce the write energy consumption of MLC PCM significantly. Meanwhile, a segmentation strategy is proposed to further improve the write performance with our coding scheme. A series of analyses and experiments was conducted to evaluate the capability of the proposed scheme. The results show that the proposed scheme can reduce 6.2–17.1% energy consumption and 3.2–11.3% write latency under six representative benchmarks, compared with the existing well-known schemes.

The advancement of nonvolatile memory (NVM) technology reduces the cost-per-unit of solid-state drives (SSDs). Flash memory-based SSDs have become ubiquitous because they provide better performance and energy efficiency than hard disk drives. However, it suffers from wear-out problems caused by the out-of-place updates that limit its lifetime. Log-structured merge tree (LSM-tree) is a level-based data structure that is widely used in many database systems because it eliminates the random write operations to the storage devices. By transferring the random write operations into sequential write operations, the write performance of hard disk drives can be improved. However, LSM-tree is not efficient for SSDs because it is not aware of the access characteristics of flash memory. Moreover, the level-based indexing strategy of the LSM-tree significantly shortens the lifetime of SSDs because the data must be frequently updated due to the compaction operations between different levels. In contrast to many previous works that focus on alleviating the write amplification on SSDs for the database systems implemented by LSM-tree, we propose LLSM, a lifetime-aware wear-leveling for LSM-tree on NAND flash memory with open-channel SSD. By considering the data access frequency of the LSM-tree between different levels, LLSM rethinks the block allocation strategy during the compaction to evenly erase all the blocks of SSD storage devices, prolonging the SSD lifetime. Moreover, a proactive swapping strategy is designed to reorganize the data blocks for resolving the potential wear-leveling issues caused by the behaviors of the LSM-tree. The extensive experiments show that the results of lifetime improvement are encouraging.

In the era of the Internet of Things (IoT), wearable IoT devices become popular and closely related to our life. Most of these devices are based on the embedded systems that have to operate on limited energy resources, such as batteries or energy harvesters. Therefore, energy efficiency is one of the critical issues for these devices. To relieve the energy consumption by reducing the total accesses on memory and storage layers, the technologies of storage-class memory (SCM) and data compression techniques are applied to eliminate the data movements and squeeze the data size, respectively. However, the information gap between them hinders the cooperation among the two techniques for achieving further optimizations on minimizing energy consumption. This work proposes a write-friendly arithmetic coding with joint managing both techniques to achieve energy-efficient non-volatile memory (NVM) systems. In particular, the concept of "ignorable bits" is introduced to further skip the write operations while storing the compressed data into SCM devices. The proposed design was evaluated by a series of intensive experiments, and the results are encouraging.