This article presents the concept of digital signal processing (DSP) systems implemented in FPGA (Field-Programmable Gate Array) devices, utilizing Dynamic Partial Reconfiguration (DPR) mechanisms. It describes hardware architectures that enable selective replacement of logic configuration fragments in real time. Applications of DPR are proposed for the implementation of Fast Fourier Transform (FFT), adaptive filtering, and sound signal synthesis, where the choice of algorithm and its parameters can be dynamically adjusted based on the quality requirements of the processed signal and hardware resource constraints. Additionally, the use of adaptive mechanisms, including artificial intelligence, is discussed as a means of supporting the configuration selection process based on quality test results such as Signal-to-Noise Ratio (SNR), latency, processing time and energy consumption. The article explores the potential of using evolutionary algorithms, large language models (LLMs), and reinforcement learning for the generation and optimization of hardware configurations. The integration of the hardware layer (Intel and Xilinx FPGA) with the software layer is also presented, using Tool Command Language (TCL) scripts and AI systems. Methods for evaluating the quality of DSP algorithm implementation are proposed. The presented solutions make it possible to build digital signal processing systems that automatically adapt their hardware architecture to improve signal processing quality while minimizing resource usage.

The article presents the concept and implementation of an extended Forth language model, dedicated to digital signal processing (DSP) tasks. The classical FORTH language has been enhanced with additional data structures, including FIFO_IN, FIFO_OUT, a temporary stack (TEMP), and two configurable generators (G1 and G2) with support for offsetting, automatic incrementing, looping, and data mirroring. The model was implemented in the MATLAB environment as a Forth interpreter capable of collecting instruction execution statistics. As part of the study, an autocorrelation algorithm was implemented in two variants: the classical (dual-stack) version and the extended version. The conducted experiments demonstrated that the extended variant significantly reduces the number of operations required to execute the same algorithm. The proposed model may serve as an intermediate stage prior to hardware implementation (e.g., on FPGA platforms).

The article presents the concept of a universal DSP core, enabling the creation of systems compliant with various processing architectures, such as Single Instruction, Multiple Data - SIMD, Multiple Instruction, Multiple Data - MIMD. The aim was to facilitate a simpler and faster configuration and programming process for complex and more efficient signal processing systems, while minimizing the need for hardware description languages. The architecture and instruction set for the DSP core are described, allowing for simultaneous addressing of multiple operands in a single instruction. Unidirectional signal flows between cores are proposed, resulting in a reduction of connections and increased performance. The testing process and comparison of results with computations performed in Matlab are described. The paper points out future research directions, such as hardware optimization, increasing the number of cores, developing floating-point computations, and modular system construction. The proposed solutions can significantly impact the efficiency and flexibility of future signal processing systems.

The article discusses the general issues of implementing pipelined and iterative algorithms. These are typical solutions for engineering algorithms implemented in hardware like reprogrammable systems. The authors focused on the implementation of such algorithms in field-programmable gate array (FPGA) circuits. Key aspects and advantages of pipelined processing were discussed. The focus was on an example CORDIC algorithm. Analyses of the iterative implementation using the ALTERA_CORDIC library were performed. Key parameters such as frequency and circuit occupancy were measured. Also, the obtained results were compared with the exact values - the errors were determined. Realizations based on 8-, 12- and 16-bits of fractional in fixed-position notation were analyzed.

The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a Field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues.

The article discusses the possibilities of measuring electrical energy consumption using selected modules. Several IoT devices and typical installation modules (for electrical switchboards) are presented. The authors applied one of the modules (three-phase) to measure energy consumption by an elevator located in a public building. Weekly and daily charts (cumulative and with 10-minute measurement periods) are presented. The collected measurement data are analyzed. Based on the results, potential savings associated with the continuous operation of the elevator system (mainly at night) - lack of sleep/standby function are determined. It is estimated that potential reduction in electrical energy consumption by the elevator could be up to 18.5% (on a weekly basis).

The article deals with the issue of stabilizing the frame position of the shot in long time astrophotography. The authors described this issue from the point of view of guiding a telescope following of the sky, and also in terms of the possibility of supporting this process with digital signal processing using paraunitary filters. The procedure for obtaining a 2D paraunitary system from an initial (preset) filter is presented. An attempt is made to verify the data that can be obtained from individual outputs of paraunitary systems. Several example filters were shown and their operation was tested on a selected image of a real astronomical object from the telescope's guide camera. Based on the output images obtained (from three paraunit systems), the possibility of their further use in practice was evaluated.

The article addresses the virtualization of network functions and services for sharing with local and national operators. Reference was made to services for campus units (universities), where integration of services is also important. Consideration was given to the possibility of expanding interuniversity cooperation in IT infrastructure and services. The authors were identified a number of important issues from the point of view of academics. Opportunities for development were demonstrated with an indication of the key advantages and disadvantages of virtualization. The focus was on optimization opportunities with particular attention to reducing personnel, hardware and energy costs, as well as security and redundancy issues. Conditions for a conceptual (prototype) workstation were discussed. Subsequent research steps were presented, including implementation testing and analysis of the required network infrastructure. All aspects take into account the possibility of collaboration between units (e.g., academic units) through the introduction of virtualization and shared services. The article provides an overview of the solutions, indicating advantages and disadvantages, and presents conceptual possibilities for the development and implementation of selected solutions.

Abstract In the article, a low sensitivity synthesis algorithm of a non‐separable N‐ dimensional ( N ‐D) finite impulse response filter implemented in Field Programmable Gate Arrays (FPGA) is proposed. The synthesis and implementation algorithms determine a pipelined non‐separable N ‐D finite impulse response filter structure consisting of fast Givens rotator structures. The filter transfer function is expressed as a function of N independent 1‐D orthogonal transfer functions in each of N directions to avoid difficult, multi‐dimensional equation computation. The rotator structure is obtained using the CORDIC algorithm. The proposed synthesis algorithm was used to design and optimise the structure of the Laplacian of Gaussian (LoG) 3‐D filter. The obtained filter was implemented in FPGA IC and its parameters, sensitivity, processing time and signal‐to‐quantisation noise ratio, were simulated and measured. The assessed results were compared with the theoretical analysis of the filter parameters. In order to verify the advantages of the proposed filtering solution, the parameter results were compared with the results of the convolution direct implementation and the orthogonal/non‐orthogonal state‐space implementation of the LoG 3‐D filter.

In the paper, the design and implementation of DSP systems with the use of modern computing and data processing methods are presented. The parallel processing and pipeline implementation of calculations as well as a number of solutions in the field of modern processing techniques, such as genetic algorithms, are proposed. New possibilities and approach to designing and implementing DSP systems in the field of cloud computing are also discussed.

In the paper, the important role of tools and distributed IT resources in the dynamic development of astrophysics, astronomy, and space exploration are discussed. New possibilities and approaches to conducting research in the field of astronomy and astrophysics with the use of cloud computing and advanced data visualization techniques are also presented. Finally, some examples of the use of digital sky survey databases in scientific research are shown.

A novel algorithm for the realisation of an orthogonal digital system performing three‐dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state‐space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field‐programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct‐form structure consisting of adders, multipliers, and delay elements.