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Andrew Richard Martin

dblp:187/2188 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Processor architecture and microarchitecture · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit		 0.011965
A Shiftrix for High-Speed Multiplication · IEEE Trans. Electron. Comput. 1965
Integrated circuit design › digital circuit design › arithmetic circuit design
parallel multiplier		 0.011965
A Shiftrix for High-Speed Multiplication · IEEE Trans. Electron. Comput. 1965
Integrated circuit design
digital circuit design		 0.011965
A Shiftrix for High-Speed Multiplication · IEEE Trans. Electron. Comput. 1965
YearPublicationVenuePosition
1989 The concurrent assignment representation of synchronous systems
Andrew Richard Martin, John V. Tucker
 Parallel Comput.1
1965 A Shiftrix for High-Speed Multiplication
abstract
The concept of the shiftrix matrix is due to Dr. G. Estrin [1] of the UCLA Department of Engineering. In broad terms the shiftrix is a device for speeding up the multiplication operation in computers by making use of complete parallelism in the shifting operation to reduce the total shifting time to a negligible value. A similar device to accomplish the same purpose has been devised by Richards [2].
Andrew Richard Martin, Allen B. Rosenstein
 IEEE Trans. Electron. Comput.1