Memory bandwidth bottlenecks severely restrict parallel access of data elements from data arrays. To realize high throughput out of a relatively low bandwidth, memory partitioning algorithms have been proposed to separate data arrays into multiple memory banks, from which multiple data can be accessed in parallel. However, previous partitioning schemes only considered the case of single-pattern and single-array. In the case of multipattern and multiarray, the previous partitioning schemes will use too much time to find a partition solution and cause excessively high storage overhead. In this paper, we propose an efficient two-step memory partitioning strategy for multipattern data access in multiple arrays. First, a fast, low complexity and low overhead difference-based data splitting algorithm provides a multibank solution for multiple patterns access. Then an area-efficient bank merging algorithm merges those partitioned banks from different arrays which satisfy conflict-free requirement in order to reduce the area overhead caused by partitioning. Experimental results show that our data splitting algorithm saves up to 83.0% in searching time and reduces 39.4% storage overhead compared to the state-of-the-art approaches. With the further optimization of area-efficient bank merging, the memory area overhead are saved up to 18.9% and the total partitioning time are saved up to 45.6%.

Spin-transfer torque random access memory (STT-RAM) has been proposed to be an excellent candidate for substituting traditional memory due to its fascinating features such as high density and low power. Memory partitioning is an efficient strategy to overcome the obstacle of memory bandwidth limiting speed of parallel data access. However, the performance is unsatisfactory, while previous memory partitioning methods are applied to STT-RAM, since they have no regard for the problem of read disturbance. In this paper, a disturbance aware memory partitioning (DaMP) method for STT-RAM is proposed. The experimental results show DaMP outperforms state-of-the-art method in terms of bank number, storage overhead, performance and searching speed.

High-Level Synthesis (HLS) has been widely recognized as an efficient compilation process targeting FPGAs for algorithm evaluation and product prototyping. However, the massively parallel memory access demands and the extremely expensive cost of single-bank memory with multi-port have impeded loop pipelining performance. Thus, based on an alternative multi-bank memory architecture, a joint approach that employs memory-aware force directed scheduling and multi-cycle memory partitioning is formally proposed to achieve legitimate pipelining kernel and valid bank mapping with less resource consumption and optimal pipelining performance. The experimental results over a variety of benchmarks show that our approach can achieve the optimal pipelining performance and meanwhile reduce the number of multiple independent memory banks by 55.1% on average, compared with the state-of-the-art approaches.

To realize high throughput out of a relatively low bandwidth, memory partitioning algorithms have been proposed to separate data arrays into multiple memory banks, from which multiple data can be accessed in parallel. However, previous partitioning schemes only considered the case of single-pattern and single-array. In this paper, we propose an efficient two-step memory partitioning strategy for multi-pattern access in multiple multidimensional arrays. First, a fast, low complexity and low difference-based data splitting algorithm provides a multi-bank solution for multiple patterns access. Then an area-efficiency bank merging algorithm reduce the area overhead caused by partitioning. Experimental results show that our memory splitting algorithm saves up to 83.0% in searching time finding a multi-bank solution, compared to the state-of-the-art approach and the storage overhead can be reduced by 34.5%. Meanwhile the area overheads are saved up to 18.86% and the whole partition time are saved up to 45.6% through our entire algorithm.