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Terry Ching-Hsiang Hsu

dblp:187/8975 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSecurity and privacy · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Systems and software security · 50% Authentication and access control · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Storage systems · 12% Distributed systems · 12%
Software engineering, system software, and programming languages
2 papers
Operating systems · 100%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › persistence
crash consistency
0.312017
NVthreads: Practical Persistence for Multi-threaded Applications · EuroSys 2017
Memory systems
non-volatile memory
0.312017
NVthreads: Practical Persistence for Multi-threaded Applications · EuroSys 2017
Memory systems › non-volatile memory › persistent memory
persistent memory programming
0.312017
NVthreads: Practical Persistence for Multi-threaded Applications · EuroSys 2017
Authentication and access control
access control
0.212016
Enforcing Least Privilege Memory Views for Multithreaded Applications · CCS 2016
Authentication and access control › access control
least privilege
0.212016
Enforcing Least Privilege Memory Views for Multithreaded Applications · CCS 2016
Systems and software security › memory safety
memory isolation
0.212016
Enforcing Least Privilege Memory Views for Multithreaded Applications · CCS 2016
Systems and software security
memory safety
0.212016
Enforcing Least Privilege Memory Views for Multithreaded Applications · CCS 2016
Distributed systems › fault tolerance › failure models
crash failures
0.112017
NVthreads: Practical Persistence for Multi-threaded Applications · EuroSys 2017
Storage systems
storage reliability
0.112017
NVthreads: Practical Persistence for Multi-threaded Applications · EuroSys 2017
Operating systems › system security › operating system security
kernel security
0.112016
Enforcing Least Privilege Memory Views for Multithreaded Applications · CCS 2016

Methods — techniques the papers use, named apart from their topics

thread-level persistence · 0.6non-volatile memory persistence · 0.6secure memory views · 0.5privilege separation · 0.5
YearPublicationVenuePosition
2017 NVthreads: Practical Persistence for Multi-threaded Applications
abstract
Non-volatile memory technologies, such as memristor and phase-change memory, will allow programs to persist data with regular memory instructions. Liberated from the overhead to serialize and deserialize data to storage devices, programs can aim for high performance and still be crash fault-tolerant. Unfortunately, to leverage non-volatile memory, existing systems require hardware changes or extensive program modifications.
Terry Ching-Hsiang Hsu, Helge Brügner, Indrajit Roy 0001, Kimberly Keeton, Patrick Eugster
EuroSys1
2016 Enforcing Least Privilege Memory Views for Multithreaded Applications
abstract
Failing to properly isolate components in the same address space has resulted in a substantial amount of vulnerabilities. Enforcing the least privilege principle for memory accesses can selectively isolate software components to restrict attack surface and prevent unintended cross-component memory corruption. However, the boundaries and interactions between software components are hard to reason about and existing approaches have failed to stop attackers from exploiting vulnerabilities caused by poor isolation. We present the secure memory views (SMV) model: a practical and efficient model for secure and selective memory isolation in monolithic multithreaded applications. SMV is a third generation privilege separation technique that offers explicit access control of memory and allows concurrent threads within the same process to partially share or fully isolate their memory space in a controlled and parallel manner following application requirements. An evaluation of our prototype in the Linux kernel (TCB < 1,800 LOC) shows negligible runtime performance overhead in real-world applications including Cherokee web server (< 0.69%), Apache httpd web server (< 0.93%), and Mozilla Firefox web browser (< 1.89%) with at most 12 LOC changes.
Terry Ching-Hsiang Hsu, Kevin J. Hoffman, Patrick Eugster, Mathias Payer
CCS1