Demo Data from VLDB 2026 / reviewers in the wild / expert
Anders Fogh
dblp:187/8985
· DBLP profile ↗
5ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 5
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
4 papers |
Hardware security and side channels · 84% Network security · 9% Systems and software security · 6% | |
| Software engineering, system software, and programming languages
2 papers |
Operating systems · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 100% |
Topics — the 13 heaviest of 13, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
microarchitectural attacks |
0.7 | 2 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018 |
Hardware security and side channels
microarchitectural side channel |
0.6 | 2 | 2019 | Page Cache Attacks · CCS 2019 Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR · CCS 2016 |
Hardware security and side channels › side-channel attack › cache side-channel attacks
cache timing attack |
0.4 | 1 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 |
Network security
covert channel |
0.4 | 1 | 2019 | Page Cache Attacks · CCS 2019 |
Hardware security and side channels
side-channel attack |
0.4 | 1 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 |
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre |
0.4 | 1 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
0.4 | 1 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.3 | 1 | 2018 | Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018 |
Systems and software security › code randomization
kernel address space layout randomization |
0.2 | 1 | 2016 | Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR · CCS 2016 |
Hardware security and side channels › microarchitectural side channel
prefetcher side channel |
0.2 | 1 | 2016 | Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR · CCS 2016 |
Processor architecture and microarchitecture
speculative execution |
0.2 | 2 | 2019 | Spectre Attacks: Exploiting Speculative Execution · IEEE Symposium on Security and Privacy 2019 Meltdown: Reading Kernel Memory from User Space · USENIX Security Symposium 2018 |
Operating systems › resource management › memory management
virtual memory |
0.2 | 2 | 2019 | Page Cache Attacks · CCS 2019 Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR · CCS 2016 |
Operating systems › system security › operating system security › protection mechanism
address space layout randomization |
0.1 | 1 | 2019 | Page Cache Attacks · CCS 2019 |
Methods — techniques the papers use, named apart from their topics
timing measurement · 0.8return-oriented programming · 0.8fault attack · 0.8ret2dir attack · 0.5prefetch instruction · 0.5ROP · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Page Cache AttacksabstractWe present a new side-channel attack that targets one of the most fundamental software caches in modern computer systems: the operating system page cache. The page cache is a pure software cache that contains all disk-backed pages, including program binaries, shared libraries, and other files. On Windows, dynamic pages are also part of this cache and can be attacked as well, e.g., data, heap, and stacks. Our side channel permits unprivileged monitoring of accesses to these pages of other processes, with a spatial resolution of 4kB and a temporal resolution of 2µs on Linux (≤6.7 measurements per second), and 466ns on Windows 10 (≤223 measurements per second). We systematically analyze the side channel by demonstrating different hardware-agnostic local attacks, including a sandbox-bypassing high-speed covert channel, an ASLR break on Windows 10, and various information leakages that can be used for targeted extortion, spam campaigns, and more directly for UI redressing attacks. We also show that, as with hardware cache attacks, we can attack the generation of temporary passwords on vulnerable cryptographic implementations. Our hardware-agnostic attacks can be mitigated with our proposed security patches, but the basic side channel remains exploitable via timing measurements. We demonstrate this with a remote covert channel exfiltrating information from a colluding process through innocuous server requests. Daniel Gruss, Erik Kraft, Trishita Tiwari, Michael Schwarz 0001, Ari Trachtenberg, Jason Hennessey, Alex Ionescu, Anders Fogh |
CCS | 8 |
| 2019 | Spectre Attacks: Exploiting Speculative ExecutionabstractModern processors use branch prediction and speculative execution to maximize performance. For example, if the destination of a branch depends on a memory value that is in the process of being read, CPUs will try to guess the destination and attempt to execute ahead. When the memory value finally arrives, the CPU either discards or commits the speculative computation. Speculative logic is unfaithful in how it executes, can access the victim's memory and registers, and can perform operations with measurable side effects. Spectre attacks involve inducing a victim to speculatively perform operations that would not occur during correct program execution and which leak the victim's confidential information via a side channel to the adversary. This paper describes practical attacks that combine methodology from side channel attacks, fault attacks, and return-oriented programming that can read arbitrary memory from the victim's process. More broadly, the paper shows that speculative execution implementations violate the security assumptions underpinning numerous software security mechanisms, including operating system process separation, containerization, just-in-time (JIT) compilation, and countermeasures to cache timing and side-channel attacks. These attacks represent a serious threat to actual systems since vulnerable speculative execution capabilities are found in microprocessors from Intel, AMD, and ARM that are used in billions of devices. While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruction set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak. Paul C. Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas 0004, Michael Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher 0002, Michael Schwarz 0001, Yuval Yarom |
IEEE Symposium on Security and Privacy | 3 |
| 2018 | Automated Detection, Exploitation, and Elimination of Double-Fetch Bugs using Modern CPU FeaturesabstractDouble-fetch bugs are a special type of race condition, where an unprivileged execution thread is able to change a memory location between the time-of-check and time-of-use of a privileged execution thread. If an unprivileged attacker changes the value at the right time, the privileged operation becomes inconsistent, leading to a change in control flow, and thus an escalation of privileges for the attacker. More severely, such double-fetch bugs can be introduced by the compiler, entirely invisible on the source-code level. We propose novel techniques to efficiently detect, exploit, and eliminate double-fetch bugs. We demonstrate the first combination of state-of-the-art cache attacks with kernel-fuzzing techniques to allow fully automated identification of double fetches. We demonstrate the first fully automated reliable detection and exploitation of double-fetch bugs, making manual analysis as in previous work superfluous. We show that cache-based triggers outperform state-of-the-art exploitation techniques significantly, leading to an exploitation success rate of up to 97%. Our modified fuzzer automatically detects double fetches and automatically narrows down this candidate set for double-fetch bugs to the exploitable ones. We present the first generic technique based on hardware transactional memory, to eliminate double-fetch bugs in a fully automated and transparent manner. We extend defensive programming techniques by retrofitting arbitrary code with automated double-fetch prevention, both in trusted execution environments as well as in syscalls, with a performance overhead below 1%. Michael Schwarz 0001, Daniel Gruss, Moritz Lipp, Clémentine Maurice, Anders Fogh, Stefan Mangard |
AsiaCCS | 6 |
| 2018 | Meltdown: Reading Kernel Memory from User Space
Moritz Lipp, Michael Schwarz 0001, Daniel Gruss, Thomas Prescher 0002, Werner Haas 0004, Anders Fogh, Jann Horn, Stefan Mangard, Paul C. Kocher, Daniel Genkin, Yuval Yarom, Michael Hamburg |
USENIX Security Symposium | 6 |
| 2016 | Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLRabstractModern operating systems use hardware support to protect against control-flow hijacking attacks such as code-injection attacks. Typically, write access to executable pages is prevented and kernel mode execution is restricted to kernel code pages only. However, current CPUs provide no protection against code-reuse attacks like ROP. ASLR is used to prevent these attacks by making all addresses unpredictable for an attacker. Hence, the kernel security relies fundamentally on preventing access to address information. We introduce Prefetch Side-Channel Attacks, a new class of generic attacks exploiting major weaknesses in prefetch instructions. This allows unprivileged attackers to obtain address information and thus compromise the entire system by defeating SMAP, SMEP, and kernel ASLR. Prefetch can fetch inaccessible privileged memory into various caches on Intel x86. It also leaks the translation-level for virtual addresses on both Intel x86 and ARMv8-A. We build three attacks exploiting these properties. Our first attack retrieves an exact image of the full paging hierarchy of a process, defeating both user space and kernel space ASLR. Our second attack resolves virtual to physical addresses to bypass SMAP on 64-bit Linux systems, enabling ret2dir attacks. We demonstrate this from unprivileged user programs on Linux and inside Amazon EC2 virtual machines. Finally, we demonstrate how to defeat kernel ASLR on Windows 10, enabling ROP attacks on kernel and driver binary code. We propose a new form of strong kernel isolation to protect commodity systems incuring an overhead of only 0.06-5.09%. Daniel Gruss, Clémentine Maurice, Anders Fogh, Moritz Lipp, Stefan Mangard |
CCS | 3 |