This work presents a fully integrated, low-noise, CMOS reference generator capable of operating at supply voltages from 0.7 V up to 1.5 V. A 3-phase barrel shifting technique is proposed to upconvert the flicker noise, achieving an integrated noise of 19.7 μVrmsover a 10 kHz bandwidth under typical conditions (0.7 V, 27 °C), without needing bulky off-chip filters. The untrimmed reference voltage from post-layout simulations exhibits an average temperature drift of 30 ppm/°C across the full temperature range of -40 °C to 125 °C. A 2-stage switched-capacitor notch filter that is proposed, brings a 60-fold reduction in the upconverted voltage ripple, and a 40 dB reduction in thermal noise at 10kHz while resulting in an exceptional Power Supply Rejection Ratio (PSRR) of -95 dB at 50 Hz. The circuit is implemented in a 22-nm FDSOI process, occupying an area of only 0.01 mm2while consuming a power of 288 nW at the typical condition.

Activation functions (AFs) such as sigmoid and tanh play an important role in neural networks (NNs). Their efficient implementation is critical for always-on edge devices. In this work, we propose a serial-arithmetic architecture for AFs in edge audio applications using the CORDIC algorithm. The design enables to dynamically trade-off throughput/latency and accuracy, and pos-sesses higher area and power efficiency compared to conventional methods such as look-up table (LUT) and piece-wise linear (PWL)-based methods. Considering the throughput difference among the designs, we evaluate average power consumption taking into account active and idle working cycles for same applications. Synthesis results in a$\mathbf{22}\mathbf{nm}$process show that our CORDIC-based design has an area of 545.77$\boldsymbol{\mu} \mathbf{m}^{2}$and an average power of 0.69$\boldsymbol{\mu} \mathbf{W}$for a keyword spotting task, achieving a reduction of 36.92% and 71.72% in average power consumption compared to LUT and PWL-based implementations, respectively.

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10,000× memory savings to 33× energy reductions, providing chip designers with an overview of design choices for implementing efficient low power neural network accelerators.

This paper presents a detailed comparison between the two commonly used capacitive DAC architectures for 10-bit SAR ADCs: binary-weighted and split-capacitor DACs. These DAC architectures are compared based on the impact of unit-capacitor mismatch and parasitic capacitance on their linearity, area and power consumption. The split-capacitor DAC is shown to be much more sensitive to unit-capacitor mismatch and parasitic capacitances as opposed to the binary-weighted DACs. Unit-capacitor values are then calculated for the split-capacitor and binary-weighted DAC topologies under two orthogonal scenarios: (a) Fixed linearity at the expense of the area and power consumption and (b) Maximizing the linearity within a specified area budget. In-spite of requiring significantly lower number of unit elements as compared to a binary-weighted DAC, split-capacitor DAC yields a larger value of unit-capacitor and total DAC capacitance for fixed linearity scenario and conversely results in a lower effective number of bits (ENOB) for a fixed area specification. Based on our analysis, binary DAC is found to be more area and power efficient than its split capacitor counterpart.

We describe a SoC achieving zero-net-energy operation by using energy harvesting and sub-threshold design. It consists of a microcontroller for data acquisition, data processing, and communication and an energy harvester unit enabling energy-autonomous operation. The microcontroller built with latch-based design achieves robust operation in a wide frequency range from 5 kHz to 40 MHz with a minimum energy point of 2.9 pJ/cycle @ 0.375V and 21 MHz. With this SoC, the battery lifetime is extended indefinitely thanks to the energy harvesting unit, which is capable to handle output power range from sub-μW to 4.32 mW with peak conversion efficiency of 65%. The tight integration of MCU and harvester enables the development of customized firmware algorithms for energy optimized operation with very diverse energy sources.

The requirements for wearables and portable medical devices present a number of challenges in terms of integration, autonomy and connectivity, and demand a careful co-design of hardware and software to reach optimum performance. This paper addresses these challenges by way of some recent examples of ASICs designed for ECG, EIT (Electrical Impedance Tomography) and PPG (Photoplethysmography) sensors as well as for non-invasive blood pressure monitoring.