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Huijuan Dong

dblp:188/0193 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 75% Reconfigurable computing and FPGAs · 25%
Databases, data mining, and information retrieval
1 paper
Data mining · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Data mining
clustering
1.012026
A Greedy Strategy for Graph Cut · IEEE Trans. Image Process. 2026
Data mining › clustering
graph clustering
1.012026
A Greedy Strategy for Graph Cut · IEEE Trans. Image Process. 2026
Data mining › clustering
spectral clustering
1.012026
A Greedy Strategy for Graph Cut · IEEE Trans. Image Process. 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator
0.812024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024
Reconfigurable computing and FPGAs
FPGA accelerator
0.812024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.812024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
sparse CNN accelerator
0.812024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024
Machine learning › Efficient and distributed learning
model compression
0.212024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024
Machine learning › Efficient and distributed learning › model compression › pruning
weight pruning
0.212024
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs · ACM Trans. Archit. Code Optim. 2024

Methods — techniques the papers use, named apart from their topics

winograd minimal filtering · 1.5relative column encoding · 1.5cross-domain pruning · 1.5normalized cut · 1.0greedy merging · 1.0eigendecomposition · 1.0
YearPublicationVenuePosition
2026 A Greedy Strategy for Graph Cut
abstract
We propose a novel Greedy Graph Cut (GGC) algorithm to address the graph partitioning problem. The algorithm begins by treating each data point as an individual cluster and iteratively merges cluster pairs that maximize the reduction in the global objective function until the desired number of clusters is achieved. We provide a theoretical proof of the monotonic convergence of the objective function values throughout this process. To improve computational efficiency, the algorithm restricts merging operations to adjacent clusters, resulting in a computational complexity that scales nearly linearly with the sample size. A significant advantage of our greedy approach is its deterministic nature, which ensures consistent results across multiple runs. This stands in contrast to many existing algorithms that are sensitive to random initialization effects. We demonstrate the effectiveness of the proposed algorithm by applying it to the Normalized Cut (N-Cut) problem, a well-studied variant of graph partitioning. Extensive experimental results show that GGC consistently outperforms the conventional two-stage optimization approach-which involves eigendecomposition followed by k-means clustering-in solving the N-Cut problem. Furthermore, comparative analyses reveal that GGC achieves superior performance compared to several state-of-the-art clustering algorithms.
Shenfei Pei, Huijuan Dong, Nianci Guan, Zhongqi Lin, Feiping Nie 0001, Xudong Jiang 0001, Zengwei Zheng
IEEE Trans. Image Process.2
2024 Meta-Regulation: An ideal alternative to the primary responsibility as the regulatory model of generative AI in China
Huijuan Dong, Junkai Chen
Comput. Law Secur. Rev.1
2024 Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs
abstract
Convolutional Neural Networks (CNNs) can benefit from the computational reductions provided by the Winograd minimal filtering algorithm and weight pruning. However, harnessing the potential of both methods simultaneously introduces complexity in designing pruning algorithms and accelerators. Prior studies aimed to establish regular sparsity patterns in the Winograd domain, but they were primarily suited for small tiles, with domain transformation dictating the sparsity ratio. The irregularities in data access and domain transformation pose challenges in accelerator design, especially for larger Winograd tiles. This paper introduces “Winols,” an innovative algorithm-hardware co-design strategy that emphasizes the strengths of the large-tiling Winograd algorithm. Through a spatial-to-Winograd relevance degree evaluation, we extensively explore domain transformation and propose a cross-domain pruning technique that retains sparsity across both spatial and Winograd domains. To compress pruned weight matrices, we invent a relative column encoding scheme. We further design an FPGA-based accelerator for CNN models with large Winograd tiles and sparse matrix-vector operations. Evaluations indicate our pruning method achieves up to 80% weight tile sparsity in the Winograd domain without compromising accuracy. Our Winols accelerator outperforms dense accelerator by a factor of 31.7× in inference latency. When compared with prevailing sparse Winograd accelerators, Winols reduces latency by an average of 10.9×, and improves DSP and energy efficiencies by over 5.6× and 5.7×, respectively. When compared with the CPU and GPU platform, Winols accelerator with tile size 8× 8 achieves 24.6× and 2.84× energy efficiency improvements, respectively.
Kunpeng Xie, Ye Lu 0004, Xinyu He 0002, Dezhi Yi, Huijuan Dong, Yao Chen 0008
ACM Trans. Archit. Code Optim.5