Compute-in-memory (CiM) has become a promising candidate for edge AI by reducing data movements through insitu operations. However, this emerging computational paradigm also poses the vulnerability of model leakage as the weights are stored in plaintext for computing. While prior works have explored lightweight encryption methods, CiM is usually considered a separate module instead of a system component, leaving the origin of keys unclear and unprotected. Physical unclonable functions (PUFs) offer a potential origin of keys, but a comprehensive framework for securing key generation and delivery remains lacking. Besides, the complementary ciphertext storage incurs substantial costs and degrades the performance. This work proposes PUFiM, a robust and efficient security solution for edge computing based on ferroelectric FETs (FeFETs). For the first time, a strong PUF is synergized with CiM to enable authentication, key generation, and encrypted computations within a unified array for comprehensive protection. To achieve this synergization, a high-density hybrid storage and computation approach combining PUF and weight bits via multi-level cell (MLC) FeFETs is proposed. Besides, two PUF enhancement techniques and a novel mapping scheme are developed to improve security and efficiency further. Results show that PUFiM withstands PUF modeling attacks with up to $\mathbf{1 0 M}$ samples. Moreover, PUFiM reduces the inference accuracy by $\gt 60 \%$ under 95% key leakage and achieves $\gt 9.7 \times$ compute density and $\gt 1.2 \times$ energy efficiency improvement compared with the state-of-the-art SRAM/NVM secure CiMs.

ABSTRACT As manufacturing faces evolving customer demands, the integration of Industrial Internet of Things (IIoT) networks is crucial for enhancing production flexibility. In this context, the Seru Production System (SPS) has emerged as a highly adaptable production mode and emphasizes the strategic assignment of cross‐trained workers, particularly in hybrid configurations combining divisional and rotating serus. This paper proposes a novel bi‐objective mathematical model incorporating learning effects to minimize makespan and balance workloads among workers. With the development of Artificial Intelligence Generated Content (AIGC) empowered big models, new breakthroughs have emerged in industrial manufacturing decision‐making. These models utilize deep learning for foundational content processing and leverage reinforcement learning to optimize strategies. This process provides robust support for achieving efficient decision optimization. Building on the concepts of AIGC big models training, this study employs reinforcement learning to refine the results of multi‐objective genetic algorithms, thereby improving the solution capability of the bi‐objective model. Experimental results demonstrate that the proposed algorithm effectively provides optimal strategies for tuning crossover and mutation operations. Additionally, numerical experiments offer insights into the formation of hybrid SPS configurations.

Hyperdimensional computing (HDC) is an emerging paradigm that employs hypervectors (HV s) to emulate cognitive tasks. In HDC, the most time-consuming and power-hungry process is encoding, the first step that maps raw data into HV s. There have been non-volatile memory (NVM) based computing-in-memory (CiM) HDC encoding designs, which exploit the intrinsic HDC characteristics of high parallelism, massive data, and robustness. These NVM-based CiMs have shown great potential in reducing encoding time and power consumption. Among them, the ferroelectric field-effect transistor (FeFET) based designs show ultra-high energy efficiency. However, existing FeFET-based HDC encoding designs face the challenges of energy -consuming current-mode addition, inefficient HV storage, limited endurance, and single encoding method support. These challenges limit the energy efficiency, lifetime, and versatility of the designs. This work proposes an energy-efficient charge-domain FeFET-based in-memory HDC encoder, i.e., CafeHD, with extended lifetime, good versatility, and comparable accuracy. Area-efficient charge-domain computing is proposed in HDC encoding for the first time, which enables CafeHD with ultra-low power and high scalability. An HV merging technique is explored to improve the performance. A low-cost partial MAJ interface is also proposed to reduce writes. Besides, CafeHD also supports two widely used encoding methods. Results show that CafeHD on average achieves 10.9×/12.7×/3.5× speedup and 103.3×/21.9×/6.3× energy effi-ciency with ~84 % write times reduction and similar accuracy compared with the state-of-the-art ReRAM/PCMlFeFET-based CiM design for HDC encoding, respectively.

Nonvolatile memory (NVM)-based computing-in-memory (CiM) has shown promising prospects in deep neural network (DNN) inference at the edge thanks to its nonvolatility and high density. Moreover, most NVMs support multi-level cell (MLC) storage, which can further boost energy efficiency and storage density. However, MLC NVM-based CiMs suffer from degraded accuracy due to device nonidealities, including large variations, nonlinear current distribution, and state drifts. Although prior works have explored various mitigation measures, such as hybrid SLC/MLC, write-and-verify, and local recovery units, the substantial costs from software support, energy, latency, and area still limit the performance. Therefore, the tradeoff between inference accuracy, storage density and compute density has become a vital challenge in NVM-based CiMs.

Tabular data are a widely used format in data science, and tree-based Machine Learning (ML) models are powerful tools and outperform Deep Neural Network (DNN) with higher accuracy for tasks on tabular data. However, computing multiple trees on massive tabular data via conventional von Neumann architectures suffers from irregular memory accesses. Prior work utilizes Analog Content Addressable Memories (ACAMs) to gain great speedup, but the analog matching method is vulnerable to device and voltage variations, and the limited density of 2D memory makes frequent data movement still inevitable for large-scale tabular data.

Ferroelectric Field Effect Transistors (FeFETs) have spurred increasing interest in both memories and computing applications, thanks to their CMOS compatibility, low-power operation, and high scalability. However, new security threats to the FeFET-based memories also arise. A major threat is the power analysis side-channel attack (P-SCA), which exploits the power traces of the memory access to obtain data information. There have been several effective efforts on resistive nonvolatile memories (NVMs), but they fail to meet the requirements for secure FeFET-based memories due to the different capacitive FeFETs load. Directly applying these existing countermeasures to the P-SCA protection for FeFETs induces huge challenges, especially for the balance between power side-channel resistance and corresponding overheads. To address this issue, we leverage the unique features of FeFETs and propose ProtFe , namely the protection methods for FeFET-based memories, including the pipelined multi-step write strategy ( PiMWrite ) and the split array design ( SpA ). PiMWrite is proposed for general FeFET-based memories, and inserts specially designed intermediate states to mitigate information leakage with pipelined steps to reduce overheads. SpA is proposed for custom FeFET-based memories, and simultaneously writes two split portions of the array with shared minimized peripherals to go beyond the balance between security and overheads. Simulation results show that PiMWrite expands the search space of a single power trace to 21× and involves nearly zero hardware penalties. SpA presents 33× search space improvement with negligible latency, 0.6% area, and only 7.1% energy overhead. ProtFe achieves improved balance between security and overheads, compared with the state-of-the-art works.

The concept of multi-level cell (MLC) enabled by emerging memory device technologies has introduced new opportunities for memory density improvement, including in the cache scenarios with some high-endurance technologies. However, the access latency of different bits within an MLC memory cell is inherently nonuniform, which raises challenges in utilizing the MLC technology for low-latency cache. To exploit the access performance of the MLC cache, the key is identifying the hot data blocks and mapping them to fast MLC bits. Prior works perform the hot/cold data management based on block-wise access patterns with considerable hardware overheads. Inspired by the memory hierarchy, this work proposes a new concept of in-cell hierarchical victim cache as embedded memory and systematically presents the cache architecture, operating mechanism, design space exploration, optimizations, and evaluations. By utilizing the slow bits as the victim buffer, lower hit latency with low implementation overheads is achieved. Based on the in-cell victim cache, two optimization techniques, namely selective victim retrieval, and victim-bypassing write (VBW) are proposed, to further improve performance and prolong cache endurance, respectively. Evaluation results show that the MLC victim cache significantly improves the average system performance by 20.2% over conventional MLC cache and achieves 98% performance of the upper bound implemented with 2x memory cells SLC. The proposed VBW also reduces energy consumption by 21% and improves lifetime by over 80%, showing a new promising dimension for future MLC cache design.

With the mass deployment of computing-intensive applications and delay-sensitive applications on end devices, only adequate computing resources can meet differentiated services' delay requirements. By offloading tasks to cloud servers or edge servers, computation offloading can alleviate computing and storage limitations and reduce delay and energy consumption. However, few of the existing offloading schemes take into consideration the cloud-edge collaboration and the constraint of energy consumption and task dependency. This paper builds a collaborative computation offloading model in cloud and edge computing and formulates a multi-objective optimization problem. Constructed by fusing optimal transport and Policy-Based RL, we propose an Optimal-Transport-Based RL approach to resolve the offloading problem and make the optimal offloading decision for minimizing the overall cost of delay and energy consumption. Simulation results show that the proposed approach can effectively reduce the cost and significantly outperforms existing optimization solutions.

The existing satellite communication systems suffer from traditional design, such as slow configuration, inflexible traffic engineering, and coarse-grained Quality of Service (QoS) guarantee. To address these issues, in this paper, we propose SERvICE, a Software dEfined fRamework for Integrated spaCe-tErrestrial satellite Communication, based on Software Defined Network (SDN) and Network Function Virtualization (NFV). We first introduce the three planes of SERvICE, Management Plane, Control Plane, and Forwarding Plane. The framework is designed to achieve flexible satellite network traffic engineering and fine-grained QoS guarantee. We analyze the agility of the space component of SERvICE. Then, we give a description of the implementation of the prototype with the help of the Delay Tolerant Network (DTN) and OpenFlow. We conduct two experiments to validate the feasibility of SERvICE and the functionality of the prototype. In addition, we propose two heuristic algorithms, namely the QoS-oriented Satellite Routing (QSR) algorithm and the QoS-oriented Bandwidth Allocation (QBA) algorithm, to guarantee the QoS requirement of multiple users. The algorithms are also evaluated in the prototype. The experimental results show the efficiency of the proposed algorithms in terms of file transmission delay and transmission rate.

Existing satellite communication has a low efficiency due to the inherent defects of the traditional design, i.e., coarsegrained control, and long configuration delay. In some previous work, researchers developed Software Defined Satellite Networks (SDSN). We reconsidered many characteristics equipped in satellite links, and deployed SDSN in the prototype by leveraging Delay Tolerant Network (DTN) and OpenFlow. However, it is necessary to develop a theoretical tool for this new network architecture to evaluate its performance. In this paper, we propose such an analytical model for SDSN using the queueing model. In particular, the Jackson's theorem is adopted to model the communication between a controller and forwarding nodes, and the store-and-forward process. The comparisons between the numerical and experimental results indicate that the proposed model is able to accurately evaluate the performance of SDSN, and will provide great benefits for the further related researches.