With the rapid development of the Internet of Things (IoT), piezoelectric energy harvesting has emerged as a highly promising power solution for autonomous IoT devices. To increase the extracted energy from the harvesters, various rectifiers have been developed. Bias-flip rectifiers, one of the most widely used rectifiers, utilize extra components to periodically flip the voltage across the harvester to achieve higher output power. This work proposes a bias-flip rectifier with an energy investment technique to boost the total harvesting power. By optimizing the energy invested from the load to the harvester and the loading conditions, the circuit can achieve higher FoM compared to conventional SSHI rectifiers under the same configurations. The proposed circuit was designed in a 180-nm BCD process, the simulation results show a 5.97 X energy enhancement compared to a full bridge rectifier (FBR) and a 1.2 X enhancement compared to conventional synchronized switch harvesting on inductor (SSHI) rectifiers.

A single transmitter source can power multiple ultrasound piezoelectric transducers to enhance the harvested power; however, the received ultrasonic signals vary in phase and amplitude across each element. This paper introduces a fully integrated, high-frequency SSHC rectifier tailored for miniaturized multi-piezo implants to efficiently harvest power at variable phase offsets with a compact form factor. The design incorporates a novel phase-splicing flipping capacitor-sharing technique between all four ultrasound piezoelectric transducers to improve area efficiency. The proposed 4-stage SSHC rectifier can harvest 5.94x more power than a full bridge rectifier operating at a high ultrasonic excitation frequency of 780 kHz. The proposed system was designed using 180-nm BCD process technology for a 2x2 piezoelectric transducer array, with each element featuring an internal capacitor (CP) of 63.7pF.

This paper presents a monolithic single-stage, 4-phase switched-capacitor (SC) hybrid boost converter with 11-to-$20\times $voltage conversion ratios (VCRs). The 4-phase operating SC hybrid topology is proposed to achieve high VCRs with only three flying capacitors and one inductor. With the SC topology, the average inductor current and the inductor current ripple are much reduced, releasing both power loss and size requirement for the inductor. A four-phase pulse width modulation (PWM) controller is proposed. A successive ramp generation scheme ensures identical pulse widths across three consecutive phases. A driver-assisted auxiliary charge pump provides sufficient driving voltages for the high-side driver and simplifies the overall circuitry. The proposed hybrid boost converter was implemented in a$0.18~\mu $m process. The measurement results show that the converter achieved a 20-24V output voltage range with a 1.2-1.8 V input voltage. 76.7% peak efficiency was achieved at$13\times $VCR and power density was 12 mW/mm3.

A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.

A triboelectric nanogenerator (TENG) is a new transducer utilizing contact electrification and electrostatic induction to transform mechanical energy into electric energy. Due to its high energy density and flexibility, it can be employed to make electronic devices self-powered by harvesting ambient mechanical energy in many application scenarios, such as biomedical devices, wearable electronics, and Internet-of-Things (IoT) sensors. However, due to the time-varying and low internal capacitance of a TENG, it is challenging to extract electrical energy from it. Hence, good power conversion techniques are crucial in TENG energy harvesting systems. Currently, studies on dedicated integrated power conversion techniques are very limited. Due to the exponentially increasing research interests in TENG, a comprehensive study on the TENG energy harvesting system, emphasizing integrated-circuit (IC) power conversion techniques, is urgently needed. This paper summarizes and compares the state-of-the-art triboelectric energy harvesting systems, focusing on different power conversion techniques for output power enhancement. Some techniques, which have been widely used in other relevant energy harvesting systems, are also mentioned to inspire innovative design strategies for TENG systems.

High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.

This paper presents a boost converter for thermo-electric energy harvesting with photovoltaic (PV)-assisted startup. The converter employs a new two-phase startup architecture and the PV cell is used in the first phase to provide an initial high voltage for startup. This high voltage drives the boost converter to charge a startup capacitor, which powers the main control block to continue self-startup in phase 2. The proposed system is designed and simulated in a $0.18\mu{\mathrm{m}}$ BCD process. The simulations show successful cold-start from 10 mV thermoelectric voltage. In addition, maximum power point tracking and zero current switching techniques are adopted in the system to achieve 91% peak efficiency. The proposed system can finish the cold-start within 250 ms.

Owing to the advancement of vibration energy harvesting technology, many motion-powered battery-free Internet of things (IoT) applications have been reported in recent years. Since the ambient energy is usually weak, these IoT devices (a) mostly operate in intermittent or burst mode. The operation of these devices heavily depends on the level of stored energy. Conventional energy-aware solutions are carried out based on discrete general-purpose comparators or analog-to-digital converters (ADC) inside the system on chip (SoC) to monitor the storage level. Their power consumption is considerable in a low-power system. This paper presents a new energy-aware circuit, which can wake up or turn off the IoT devices according to the stored energy. Its standby quiescent current is at the sub-$\mu$A level. The proposed circuit also provides a regulated output voltage for IoT applications. This design is built with discrete analog components. It is low cost and has high feasibility. It is compatible with different kinds of micro-power generators.

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

An ultra-low-startup-voltage thermoelectric energy harvesting system assisted by a piezoelectric generator (PEG) is presented in this paper. When the energy harvesting system is implemented in a place where there is mechanical vibration, the associated PEG can generate a stable clock signal and drive the boost converter to start from the cold state even at extremely low thermoelectric generator (TEG) voltage. The proposed system is designed and simulated in a 180-nm BCD process. The simulations show that the proposed system can start the TEG system from the cold state from as low as 10 mV of TEG voltage while keeping a 63.9% efficiency. The peak power conversion efficiency is achieved at 74.9% when the TEG voltage is 50 mV.

Ultrasonic wireless power transfer (WPT) has been proved to be a promising approach to power biomedical implants. To extract the energy generated from the transducer, a rectifier is typically required. Previous inductor-based rectifiers (SSHI and SECE) require a large off-chip inductor to achieve good performance, which is not desired for miniaturization and safety reasons. Synchronized switch harvesting on capacitors (SSHC) rectifiers have been proved to achieve high performance without inductors; however, they are mainly designed for low-frequency kinetic energy harvesting. In this paper, an improved SSHC rectifier is designed to achieve a fully integrated design with all flying capacitors implemented on-chip. The proposed SSHC rectifier can properly operate at ultrasonic excitation frequency (100 KHz) with precise switching time control and ultrafast voltage flipping techniques. In addition, an on-chip ultralow-power LDO allows the system to be self-sustained. The system is designed in a TSMC 180nm BCD technology and post-layout simulation results are presented.

Synchronized switch harvesting on inductor (SSHI) is an efficient active rectifier to extract energy generated from piezoelectric transducer in piezoelectric energy harvesting system. Unlike passive rectifiers, SSHI rectifiers require a power supply to drive synchronized switches. Unfortunately, there is no stable supply when the system starts from the cold state. Most designs let the system work as a passive full bridge rectifier (FBR) to charge power capacitor until a supply is available. However, a FBR requires high open-circuit voltage (VOC) and the FBR’s output voltage cannot go over VOC. This prevents the system from starting the SSHI rectifier if VOCis low. This paper proposes a new transducer reconfiguration design to lower the required VOCby 4 $\times$ to start up the SSHI system from the cold state. The proposed system is designed in a 0.18$-\mu$m BCD process and post-layout simulations show that the successful cold-startup under low VOCvoltage.

Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.

A nanopower highly efficient low-dropout (LDO) regulator for energy harvesting (EH) applications is presented in this paper. The LDO is fully autonomous with a bandgap reference (BGR) featuring a novel bandgap supply-switching (SS) topology, an over-voltage protection (OVP), a under-voltage lockout (UVLO) and control block to obtain stable output and robust cold-start. The system provides configurable voltage supply (1.1 $\sim$2V) for potential loads, while consuming as low as 66 nW power. The entire system achieves a peak power efficiency of 95.6% at Vout=2V and $I_{\iota_{oad}}$=100$\mu$A.

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the$2^{\mathrm{nd}}$-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8$\mu \text{W}$power.

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

Harvesting energy from environments has been a promising approach to power ubiquitously distributed Internet of Things (IoT) devices. For harvesting kinetic energy with piezoelectric transducers, synchronized switch harvesting on capacitors (SSHC) rectifiers have been demonstrated to achieve high energy extraction performance without using any inductor. In previous studies, the switched capacitors in SSHC rectifiers are chosen equal to the inherent capacitance of the piezoelectric transducer (PT) to achieve good voltage flip efficiencies at 33.3%, 50% and 66.7% for 1-, 2- and 4-stage SSHC rectifiers, respectively. However, with much larger switched capacitors and the same SMD package size, this paper finds that the voltage flip efficiency can be further increased to 50%, 66.7% and 80% for 1-, 2- and 4-stage SSHC rectifiers, respectively; as a result, the output power can be greatly increased. This paper also finds that the proposed design only requires half number of capacitors to achieve the same voltage flip efficiency for conventional SSHC rectifiers, which significantly reduces the system form factor for miniaturization.