Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today's cost/performance marketplace, modern CPU designs must effectively balance both performance and power dissipation. The choice of pipeline depth and target clock frequency has a critical impact on both of these metrics. We describe an optimization methodology based on both analytical models and detailed simulations for power and performance as a function of pipeline depth. Our results for a set of SPEC2000 applications show that, when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of our energy models. Finally, we discuss the potential risks in design quality for overly aggressive or conservative choices of pipeline depth.

Almost by definition, well-tuned digital circuits have a large number of equally critical paths, which form a so-called "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, model-to-hardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater.Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertainty-aware" mode has been implemented and applied to several high-performance microprocessor macros. Numerical results are included.

Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (η), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design we derive relations for η and supply voltage V under progressively more general situations, and incorporate η into a prior art architectural energy-efficiency criterion. Then, a more general relation is derived for the optimal balance between the architectural complexity, hardware intensity and power supply. Modified forms for these relations are obtained in special cases where the supply voltage is constrained or when clock gating is disallowed.

During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.

Article Free Access Share on Gradient-based optimization of custom circuits using a static-timing formulation Authors: A. R. Conn IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , I. M. Elfadel IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , W. W. Molzen IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , P. R. O'Brien IBM Electronic Design Automation, 11400 Burnet Road, M. S. 9460, Austin, TX IBM Electronic Design Automation, 11400 Burnet Road, M. S. 9460, Austin, TXView Profile , P. N. Strenski IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , C. Visweswariah IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , C. B. Whan IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 452–459https://doi.org/10.1145/309847.309979Published:01 June 1999Publication History 29citation367DownloadsMetricsTotal Citations29Total Downloads367Last 12 Months21Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF