An efficient all-to-all communication algorithm for torus and mesh networks, A2AT, was proposed. A2AT schedules message sending sequence so that all links are fully used by exploiting function of concurrent message transfer in the node. By using A2AT, the hop count of messages equals the maximum number of messages sharing a link in their routes for all message transfers. A2AT can therefore maintain synchronization without the need for phasing operation such as an MPI barrier. When the VOQ which is an ideal configuration for A2AT was used, communication times for mesh/torus network obtained by A2AT were roughly 1.20 and 1.09 times higher, on average, than those of the ideal times. When the networks had the minimum number of virtual channels and a small buffer, assuming a practical network, A2AT was able to reduce communication times by 12.5% and 36.0% compared with those of the conventional algorithm. When two controllers are used, A2AT reduced 28.2% and 55.7% communication time with those by A2AND on 15×15×15 (=3,375 nodes) mesh and torus networks respectively (18.6% and 44.8% in average). A2AT also reduced 15.1% and 41.9% of communication time with those by A2AND on the same mesh and torus networks respectively (14.4% and 37.5% in average) when six controllers are used.

The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.

The performance of message-passing applications depends on cpu speed, communication throughput and latency, and message handling overhead. In this paper we investigate the effect of varying these parameters and applying techniques to reduce message handling overhead on the execution efficiency of ten different applications. Using a message level simulator set up for the architecture of the AP1000, we showed that improving communication performance, especially message handling, improves total performance. If a cpu that is 32 times faster is provided, the total performance increases by less than ten times unless message handling overhead is reduced. Overlapping computation with message reception improves performance significantly. We also discuss how to improve the AP1000 architecture.

Low-latency communication is the key to achieving a high-performance parallel computer. In using state-of-the-art processors, we must take cache memory into account. This paper presents an architecture for low-latency message comunication and implementation, and performance evaluation.

A general purpose Cellular Array Processor(CAP) with distributed frame buffers for fast parallel subimage generation has been developed. CAP consists of many processor elements called cells. A cell has video memory for subimage storage, a window controller to map each subimage to an area on the monitor screen, and communication devices, in addition to ordinary microcomputer components such as MPU, RAM, and ROM. Image data in a cell is directly displayed via the video bus. The mapping pattern and the position on the screen of subimages can be changed dynamically. Various hidden surface algorithms can be implemented in CAP using mapping patterns appropriate for the algorithm.Our goal is an efficient interactive visual solid modeler. We adopted a general CSG hidden surface algorithm that enables display of both Boundary representation and Constructive Solid Geometry. A technique for hidden surface removal of general CSG models, requiring less memory space for large models in many cases, has been proposed. This technique subdivides the model into submodels by dividing the CSG tree at union nodes. Imagse of each submodel are generated by a CSG or a z-buffer algorithm. If a submodel is just a primitive, it is processed by the z-buffer algorithm, otherwise by the CSG algorithm. Hidden surface removal between submodels is done by comparing the z values for each pixel which are saved in the z-buffer.