We propose a methodology using nodal analysis techniques compatible with existing computer-aided design (CAD) tools for implementing critical threshold design rules for electromigration reliability. The concept underlying critical threshold design rules is the observation that a mechanical stress-induced backflow of metal atoms is created by electromigration in interconnect lines confined by a rigid dielectric. If the steady-state balance of these two atomic fluxes is achieved before critical electromigration damage is realized, then the line can be considered to be virtually immortal with negligible reliability risk. A design rule based on this critical threshold criterion has the potential to give designers added flexibility to use currents larger than present design rules typically allow in short interconnects.

In a high performance microprocessor such as Digital's 30O MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the interconnect segments (thus reducing their capacitance) of the distribution network while meeting certain design goals. These techniques place no restrictions on the topology of the network being sized, and have been successfully used on very large examples.