In our paper[1], there was an error in (50), which is rewritten here as

A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. 3-D self-consistent electrothermal simulations, tuned with experimentally measured electrical characteristics, were used to understand the nature of self-heating in FinFETs and calibrate the proposed model. The accuracy of the model has been demonstrated for a wide range of multifin devices by comparing it against finite element simulations. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures, which are critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability. The transient model has been used to estimate the thermal time constants of these devices and predict the sensitivity of power-to-failure to various device parameters, for both long and short pulse ESD situations. Suitable modifications to the model are also proposed for evaluating the thermal characteristics of production level FinFET (or Tri-gate FET) structures involving metal-gates, body-tied bulk FinFETs, and trench contacts.

We present a high-frequency impedance extraction method for horizontal interconnects as needed in 3-D integrated circuits (ICs), where the horizontal interconnects are sandwiched between substrate layers of possibly different electromagnetic parameters. In particular, for the first time, we develop an extension of the discrete complex images method based on a 2D, or alternatively, 3D magneto-quasi-static (MQS) vector potential Green's functions to extract analytical solutions to the series impedance (resistance and inductance) matrix elements for wire filaments. We then follow standard methods to extract the port impedance. Using the 2D approach, the series impedance per unit length of horizontal wire loops is obtained, which shows excellent accuracy (<; 1% error to Maxwell SV) and significantly improved computational cost (two orders faster than Maxwell SV). Using our 3D approach and combining the series impedance matrix from the MQS extraction engine with the capacitance matrix from an electrostatic extraction engine, we produce an electro-magneto-quasi-static impedance matrix extraction engine, which is used to extract the input impedance of a spiral inductor. In the frequency range spanning near dc to a high frequency cutoff given by four times the frequency of the maximum in the quality factor, we show that our results agree to within less than 5% and 11% deviation to the full-wave simulator HFSS, for the self and mutual loop impedance, respectively. The CPU time using our approach is 18-25× faster than HFSS. These results provide a reasonable foundation for circuit block-level impedance extraction for interconnects and inductors in 3-D integrated systems.

Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated double-electrode NEMS" structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoulli's beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models "underestimate" the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors. © Copyright 2010 ACM.

Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one of the most important reliability concerns for deep nano-scale regime VLSI circuits. Hence, aging-resilient design methodologies are necessary to address this issue in order to improve reliability, preferably with minimal impact on the area, power and performance. This work offers two major contributions to the aging-resilient circuit design methodology literature. First, it introduces a novel sensor circuit that can detect the aging of pipeline architectures by monitoring the arrival time of data signals at flip-flops. The area overhead of the proposed circuit is estimated to be less than 45% compared to that of previous approaches, which are over 95%. To ensure the accuracy of its operation, a comprehensive timing analysis is performed on the proposed circuit including the influence of process variations. As a second contribution, this work presents an innovative correction technique to reduce the probability of timing failures caused by aging. This method employs novel reconfigurable flip-flops, which operate as normal flip-flops as long as the circuit is fresh, but function as time-borrowing flip-flops once the circuit ages. This unique flip-flop design allows utilization of the advantages of the time-borrowing technique while avoiding potential race conditions that can be created by employing such a technique. It is shown via simulations that by employing the proposed design methodology, the probability of timing failures in the aged circuits can be reduced by as much as 10X for various benchmark circuits.

We present an efficient and highly accurate approach to high-frequency impedance extraction for VLSI interconnects and intentional on-chip inductors. The approach is based on a three-dimensional (3D) loop formalism that uses discrete complex images approximations applied to a quasi-magnetostatic treatment of the vector potential, resulting in closed-form expressions for the impedance matrix of current filaments in the presence of a multi-layer substrate. Populating the impedance (Z) matrix for 3D configurations of finite transverse dimensions (including non-Manhattan wires and inductors) is computationally inexpensive, and includes substrate eddy current effects that become quantitatively important in the frequency regime beyond 20 GHz which is imminent at the 45 nm technology node onwards. The accuracy, as exemplified by the magnitude of inductor impedance |Z|, is within 5% of a full-wave electromagnetic field solver for frequencies up to 100 GHz, with an order of magnitude lower computation cost. The proposed method represents a core technology for incorporation into system level extraction of analog systems consisting of multiple inductors and nearby interconnects, for CMOS on-chip circuits in the nanometer era.

This paper, for the first time, shows that the work-function variation (WFV) in emerging metal-gate devices results in significant fluctuation in the gate-oxide electric field, and hence fluctuation in bias temperature instability (BTI) characteristics (both NBTI and PBTI). We modify the existing NBTI and PBTI models in order to accurately characterize the BTI characteristics of the metal-gate devices. It is shown that the impact of the oxide electric field on threshold voltage degradation is substantially underestimated if WFV is neglected. Moreover, in FinFET devices, work-function variation induced electric field (which is independent of the gate-source bias) not only results in fluctuation in the BTI characteristics, but also causes variation in the recovery process. It is highlighted for the first time that WFV induced BTI fluctuation can have significant impact on the performance and reliability characteristics of digital circuits such as SRAM cells and Domino logic gates.

Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterally-actuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts.

In the above titled paper (ibid., vol. 28, no. 7, pp. 1047-1060, Jul. 09), there is an error in equation (17) and equation (15) should be modified. The corrections are presented here.

Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This is because to maintain an acceptable noise margin level in deep sub-100 nm technologies, large pMOS keepers must be employed, which generates substantial contention between the keeper and the pull-down network, and hence results in severe loss of performance and high power consumption. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this paper, a novel variation-tolerant keeper architecture is proposed, which is capable of significantly reducing contention and improving performance and power consumption. Using circuit simulations, the overall improved characteristics of the proposed keeper are demonstrated in comparison to those of the traditional as well as several state-of-the-art keepers. The proposed keeper exhibits the lowest delay deviation under different levels of process variations. Also, it is shown that for an eight-input or gate, in presence of 15%Vthfluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to the traditional keeper circuit.

This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. The strength of the keeper device is controlled by the differential gate voltage, which guarantees low gate-source voltage at the beginning of the evaluation phase and high gate-source voltage during rest of the time.

No abstract available.

FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. Considering these exclusive properties of FinFETs, the sources of process variations and their effects on FinFET-based circuit characteristics can be significantly different from that in bulk CMOS devices. This paper identifies a new source of random process variation due to the gate work-function variation and resulting electrical confinement in emerging high-k/metal-gate FinFET devices. In order to capture the effect of the variations on the characteristics of multifin FinFETs (considering their width quantization property), this paper also presents a new statistical framework to accurately predict the effective threshold voltage of multifin FinFET devices. This framework is subsequently used to predict the leakage profile of FinFET-based SRAM cells. Since FinFETs are optimal for ultra-low-voltage operations due to near-ideal subthreshold swing (60 mV/dec), we focus on FinFET-based SRAM (including subthreshold SRAM) design. Contrary to the low sensitivity of the static noise margin (SNM) to the width of the pull-down devices in bulk-CMOS subthreshold SRAMs, our analysis shows, for the first time, the significant impact of employing multifin pull-down devices on the SNM of subthreshold FinFET SRAMs.

Accurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass silicon success. Present commercial thermal analysis tools are incapable of simulating complex structures, particularly in the 3-D domain and are also difficult to integrate with existing design tools. Existing analytical thermal models are not perfect either: they are either not accurate enough or oversimplified. This paper uses a methodology, which exploits existing electrical resistance solvers for thermal simulation, to allow fast acquisition of thermal profiles of complex interconnect structures with good accuracy and reasonable computation cost. Moreover, for the first time, an accurate closed-form thermal model is developed. The model allows for an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace the detailed material information in non-critical regions so that complex interconnect structures can be simulated. Using these techniques, this paper demonstrates the simulation of a very complex interconnect structure (~9000 objects or 15 million meshed unknowns after first order isotropic equivalent medium replacement), which is a first time achievement in the area of interconnect thermal analysis. On the other hand, it is shown that an anisotropic equivalent medium is a much better approximation of real interconnect structures from the point of view of accuracy and computation.

Graphene is a single-atom thick layer of graphite, which is one of the well known allotropes of carbon. While Graphene is a 2-D material, it can be either rolled-up to form carbon nanotubes (CNT) or simply patterned to form graphene nano-ribbons (GNR), which essentially display 1-D transport characteristics. Due to their outstanding electrical properties, CNTs and GNRs are considered as a possible replacement for Silicon. This talk will start with a brief overview of the physics of these carbon nanomaterials, discuss various device structures--their relative advantages and drawbacks and their fabrication related challenges. It will then discuss various design challenges arising due to the chirality problem (presence of metallic CNTs in CNFETs), ambipolar conduction in both CNFET and GNRFET, edge scattering in GNRFETs, channel quantization/screening effect in CNFETs, and source/drain extension and other parasitics that play a central role in restricting the performance of these transistors well below their theoretically predicted limits. This talk will conclude with a brief discussion of the scaling implications and comparison with conventional CMOS to provide a possible roadmap into the future.

We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green's function approach with the correct quasi-static limit, a modified discrete complex images approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances that are relevant to VLSI interconnects. This approach permits the evaluation of the self-impedance and mutual-impedance of multi-conductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multilayer substrate.

Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field effect transistor (CNFET) based on tunneling principle has been proposed, which shows impressive device properties and overcomes some of the limitations of previously proposed CNFET devices. Although carbon nanotube based devices have been optimized for DC performance so far, little has been done to optimize them for high-frequency operation. In this paper, we present, detailed modeling and analysis of device geometry based intrinsic and parasitic capacitances of tunneling carbon nanotube field effect transistors (T-CNFETs) with both single nanotube as well as nanotube-array based channel. Based on the model, we analyze scaling of parasitic capacitances with device geometry for two different scaling scenarios of T-CNFETs. We show that in order to reduce the impact of parasitic capacitance, nanotube density has to be optimized. Furthermore, for the first time, we analyze various factors affecting the high-frequency/RF performance of back gated T-CNFETs and study the impact of parasitic and screening effects on the high-frequency/RF performance of these devices.

We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) and CPU time reduction (factors of seven) emerge from three different ingredients: a two dimensional Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a novel discrete dipole approximation to evaluate the magnetic vector potential. This approach permits the evaluation of the mutual impedance between two loops in terms of easily computable analytical expressions that involve the relative separations and the electromagnetic parameters of the multi-layer substrate. The results are valid for long wires, for any separation, and for frequencies up to 100 GHz.

For the first time, a new source of random threshold voltage (Vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, christened Work-Function Variation (WFV), is caused by the dependency of metal work-function on the orientation of its grains. A statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. This paper offers three major contributions for process, device and circuit designers. First, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of Vth fluctuation due to WFV. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN result in lower Vth fluctuation. Second, device engineers can benefit from the result of this work by evaluating the WFV level of various types of classical or non-classical metal-gate CMOS transistors. As an example, it is shown that FinFET transistors are less affected by WFV compared to FD-SOI and Bulk-Si devices due to their larger gate area. Third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. For instance, an SRAM cell is analyzed in the presence of Vthfluctuations due to WFV and it is shown that such variations can result in considerable performance and reliability degradation.

As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI design. Consequently, enhancing processing performance is no longer the most important factor that dominates future circuit design considerations. This paper, for the first time, proposes a systematic methodology to determine a generalized design optimization metric for simultaneously trading-off power and performance in nanometer scale integrated circuits to achieve design-specific targets. The methodology incorporates interconnect effects as well as electrothermal couplings between substrate temperature, power, and performance for nanometer scale design optimization. Implications of choosing a specific design optimization metric on power, performance, and operating temperature are illustrated and discussed. The proposed methodology is shown to provide a more meaningful optimization metric (for power-performance tradeoff analysis) and basis, with considerations of chip-level thermal management including maximum allowable operating temperature and packaging/cooling solutions. Furthermore, implications of CMOS technology scaling and parameter variations on the proposed methodology are discussed.

Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low power dynamic OR gates, SRAM cells, and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60--80% lower switching power and almost zero leakage power consumption with minor delay penalty. However, the hybrid gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that the proposed hybrid SRAM cell can achieve almost 8X lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in upto three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.

Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper provides a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale - in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale-circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3D ICs and highlights the advantages of employing hybrid carbon nanotube-Cu interconnects in both 2D and 3D designs.

While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexity of modern systems, software developers are increasingly dependent on specialized development tools such as security profilers, memory leak identifiers, data flight recorders, and dynamic type analysis. Many of these tools require full-system data which covers multiple interacting threads, processes, and processors. Reducing the performance penalty and complexity of these software tools is critical to those developing next generation applications, and many researchers have proposed adding specialized hardware to assist in profiling and introspection. Unfortunately, while this additional hardware would be incredibly beneficial to developers, the cost of this hardware must be paid on every single die that is manufactured.In this paper, we argue that a new way to attack this problem is with the addition of specialized analysis hardware built on separate active layers stacked vertically on the processor die using 3D IC technology. This provides a modular "snap-on" functionality that could be included with developer systems, and omitted from consumer systems to keep the cost impact to a minimum. In this paper we describe the advantage of using inter-die vias for introspection and we quantify the impact they can have in terms of the area, power, temperature, and routability of the resulting systems. We show that hardware stubs could be inserted into commodity processors at design time that would allow analysis layers to be bonded to development chips, and that these stubs would increase area and power by no more than 0.021mm2 and 0.9% respectively.

Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper and thereby extend the lifetime of electrical interconnects. This paper examines the state-of-the-art in CNT interconnect research and discusses both the advantages and challenges of this emerging nanotechnology.

Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance. In this paper, a novel keeper architecture is proposed which is capable of significantly reducing the contention and improving the performance and power consumption. Using circuit simulations, superior characteristics of the proposed keeper is demonstrated in comparison to those of the traditional as well as state-of-the-art keepers. It is shown that for an 8-input OR gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to traditional keeper circuit.

Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3-D technology under the influence of such thermal constraints. Using a processor-cache-memory system and carefully chosen applications encompassing different memory behaviors, the performance of 3-D architecture is compared with a conventional planar (2-D) design. It is found that the substantial increase in memory bus frequency and bus width contribute to a significant reduction in execution time with a 3-D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3-D designs than for planar 2-D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3-D than for 2-D designs. In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.

As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are beginning to impact VLSI design. Moreover, elevated substrate (junction or die) temperature strongly influences IC performance, reliability, and packaging/cooling cost. Hence, accurate estimation of substrate thermal profiles is critical. This paper presents an accurate chip-level electrothermally-aware methodology for spatial silicon substrate temperature estimation. The methodology self-consistently incorporates various electrothermal couplings arising mainly due to the strong dependence of subthreshold leakage on temperature and also employs an accurate package thermal model, to account for inhomogeneous layers and non-cubic structure, which are not considered in traditional methods. The proposed methodology becomes increasingly effective as technology scales due to increasing leakage. Furthermore, it is shown that considering realistic package thermal models not only improves the accuracy of estimating temperature distribution but also has significant implications for power estimation and hot-spot management.

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out.

As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine a generalized design metric for simultaneously optimizing power and performance in nanometer-scale integrated circuits to achieve design-specific targets while incorporating electrothermal effects. This methodology is shown to provide a more meaningful basis to compare different design choices. The implications of technology scaling and parameter variations on this thermally-aware methodology are also presented.

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization in nanometer scale designs taking all significant parameter variations into account. The relative effect of different device, interconnect and environmental variations on delay and different components of power has been studied. A probabilistic framework to optimize buffer-interconnect designs under variations has been presented and results are compared with those obtained through simple deterministic optimization. Also, statistical models for delay and power under parameter variations have been developed using linear regression techniques. Under statistical analysis, both power and performance of buffer-interconnect designs are shown to degrade with increasing amount of variations. Also, % error in power estimation for power-optimal repeater designs is shown to be significant if variations are not taken into account. Furthermore, it has been shown that due to variations, significantly higher penalties in delay are needed to operate at power levels similar to those under no variations. Finally, the percentage savings in total power for a given penalty in delay are shown to improve with increasing amount of parameter variations.

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (Vdd) and threshold (Vth) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the Vdd-Vth plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.

This paper presents a probabilistic framework for full-chip estimation of subthreshold leakage power distribution considering both within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). The results obtained under this framework are compared to BSIM results and are found to be more accurate in comparison to those obtained from existing statistical models. Using this framework, a quantitative analysis of the relative sensitivities of subthreshold leakage to P-T-V variations has been presented. For the first time, the effects of die-to-die channel length and temperature variations on subthreshold leakage are studied in combination with all within-die variations. It has been shown that for accurate estimation of subthreshold leakage, it is important to consider die-to-die temperature variations which can significantly increase the leakage power due to electrothermal couplings between power and temperature. Furthermore, the full-chip leakage power distribution arising due to both within-die and die-to-die P-T-V is calculated, which is subsequently used to estimate the leakage constrained yield under the impact of these variations. The calculations show that the yield is significantly lowered under the impact of within-die and die-to-die process and temperature variations.

The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.

Abstract: The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a suite of commercial tools in combination with a high-speed extractor based on an innovative semi-analytical method to deal with noise coupling problems, and enable RF designers to achieve a first silicon-success of their chips. The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver demonstrated. The proliferation of Mixed-Signal-SOCs leads to two seemingly contradictory requirements on design methodology: on one hand, higher levels abstraction is needed to cope with the added complexity in design, while at the same time, the shrinking process technologies

This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.

Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-uniform temperature profiles that exist along their lengths, which in turn arise due to the thermal gradients in the underlying substrate. A non-uniform temperature-dependent distributed RC interconnect delay model is proposed for the first time. The model has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.

This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in the driver capacitance and output resistance with scaling makes deep submicron (DSM) designs increasingly susceptible to inductance effects. Also, the impact of inductance variations on performance has been quantified. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues have been analyzed.

Studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperature-dependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the near-optimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling.

Presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress conditions. The results agree with experimental data and those using finite element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temperature rise in the metal wires, is included in the analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multi-level interconnects. We discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed.

This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.

Article Free Access Share on On thermal effects in deep sub-micron VLSI interconnects Authors: Kaustav Banerjee Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Amit Mehrotra Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Chenming Hu Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999Pages 885–891https://doi.org/10.1145/309847.310093Published:01 June 1999Publication History 60citation1,225DownloadsMetricsTotal Citations60Total Downloads1,225Last 12 Months111Last 6 weeks22 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF