Wireless sub-mm sized distributed brain implants have been proposed as the next frontier of Brain-Machine Interface (BMI) design to achieve untethered, high-density neural recording and stimulation. Simultaneously improving the wireless power transfer (WPT) efficiency and reducing the specific absorption rate (SAR) will be crucial for its clinical success. Towards these goals, we present an EM simulation method, a lumped equivalent circuit model, and a theoretical analysis to accurately predict the power delivered to the recording/ stimulating nodes, as well as the power dissipated in biological tissues and all other lossy elements within the system. This comprehensive framework also explains how increasing the distance between the transmit coil and the scalp can beneficially reduce the SAR without undermining the WPT efficiency. This work presents a rigorous prediction technique for transmission loss and tissue heating towards performance optimization.

A novel Brain-Machine Interface (BMI) system based on a distributed network of implantable wireless sensors was proposed. Small CMOS "Neurograin" chips (0.5x0.5 mm2) with on-chip antenna are designed to harvest near-field RF energy at ~1 GHz, and backscatter 10 Mbps BPSK modulated data asynchronously and periodically. A "Skinpatch" software-defined radio (SDR) receiver is realized on a commercial USRP running GNU Radio programs. It down-converts the reflected waves from the Neurograins and performs data recovery. In this BMI prototype demonstration, 32 Neurograins will be wirelessly powered, while a Skinpatch USRP will recover their backscattered packets in real-time.

A general method for designing a wide tuning range CMOS LC quadrature oscillators (QOSC) is introduced. A design example of a QOSC with switchable quadrature oscillation mode is presented. The effective tuning range is 89% for a 1.4 GHz example.

A tunable RF filter for interference suppression applications, using a balanced passive complex mixer and a parallel LC tank load, is presented. The circuit has very wide dynamic range and zero dc-power consumption, and is designed for cognitive radio applications in the IEEE 802.22 system.

Future generations of wireless communications are expected to place increasing burdens on the efficiency and linearity of power amplifiers, due to the use of more complex waveforms and OFDM. This has implications for the design of transmitters in portable/mobile devices as well as base stations and access points. This paper summarizes the digital techniques that can be employed to improve the performance of wireless power amplifiers

Performance trade offs of unary-R-2R and unary-binary digital-to-analog converters are presented. It is shown that for a given resolution and sampling rate, the active area of the unary-binary converter grows as the operating current of the unit cells approaches the weak inversion region. At very low-currents, the unary-R-2R architecture has a large area advantage over the unary-binary architecture for medium resolution, medium-speed applications.

An improved exact dynamic model of a fast-settling linear-in-dB automatic gain control (AGC) circuit is proposed. The explicit transient behavior is calculated for a first-order and second-order AGC loop

An all n-p-n highly linear wide-bandwidth bipolar transconductor (Gm) stage is presented based on a variation of Caprio's quad. The high-frequency (HF) linearity of the improved Gmcell is examined by a Volterra analysis. The improved Gmcell has a higher input voltage swing range than other approaches

Several new approaches are presented for the reduction of power dissipation in wireless transceivers for mobile wireless applications. In most cases, the power dissipation of the circuit can be dramatically lowered without a significant reduction in circuit dynamic range or linearity. These techniques involve the use of active bias circuits to continuously optimize the performance of the circuit under varying bias levels.

A tutorial review on the modulation-doped field-effect transistor (MODFET) and its application to ultra-low-noise, medium-power, and ultra-wide-band traveling-wave amplifiers as well as ultra-high-speed digital logic circuits is presented. It is believed that with further advances in material growth and device scaling significant improvements in cutoff frequencies, switching speed, noise, and power will be achieved in the near future.>