Stability analysis is one of the key challenges in analog circuit design. As feature sizes continue to shrink and the effect of parasitics becomes more dominant, we are forced to deal with stability analysis of increasingly complex multiloop structures with potentially hundreds of loops-a task that can no longer be dealt with using traditional methods. An automated stability checker tool that detects sources of potential ringing behavior within a reasonable turnaround time has thus been made necessary. Such a tool would not just help in debug but could also serve as a postlayout validation tool. We thus present an efficient loop finder algorithm to identify sources of ringing in large linear analog circuits. At the heart of our automated stability checker are two newly developed computationally efficient algorithms-the first to detect all poles within a given region of interest with a high degree of confidence and the second to extract second-order approximations of node impedance transfer functions given these pole locations. In this paper, we discuss these algorithms in detail, propose various optimization heuristics to further speed up the pole discovery algorithm, and then go on to develop a parallel implementation of both these underlying algorithms. It is demonstrated that these approaches together allow us to outperform the original loop finder algorithm based on direct eigen methods by two to four orders of magnitude and thus enable stability analysis of even larger extracted industrial designs than was previously possible while providing reasonable turnaround time.

Stability analysis is one of the key challenges in the design of large linear analog circuits with complex multi-loop structures. In this paper, we present an efficient loop finder algorithm to identify potentially unstable loops in such circuits. At the heart of our automated stability checker lie two newly developed computationally efficient algorithms --- the first to detect all poles within a given region of interest and the second to extract second order approximations of node impedance transfer functions given these pole locations. It is shown that the proposed technique outperforms existing stability methods by more than one order of magnitude for medium sized circuits and enables stability analysis of large extracted industrial designs which was previously infeasible.

Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time systems (operational amplifiers and other linear circuits). The methodology used allows for easy identification and diagnostics of AC-stability problems including not only main-loop effects, but also local-instability loops in current mirrors, bias circuits and emitter or source followers without breaking the loop. The results of the analysis are easy to interpret. Estimated phase margin is readily available. Instability nodes and loops along with their respective oscillation frequencies are immediately identified and mapped to the existing circuit nodes, thus offering significant advantages compared to traditional "black-box" methods of stability analysis (transient overshoot, bode and phase margin plots, etc.). The tool for AC-stability analysis is written in SKILL/spl trade/ and is fully integrated in the DFII/spl trade/ environment. Its "pushbutton" graphical user interface (GUI) is easy to use and understand. The tool can be invoked directly from a Composer/spl trade/ schematic and does not require an active Analog Artist/spl trade/ session. The tool is not dependent on the use of a specific fabrication technology or process design kit customization. It requires OCEAN/spl trade/, Spectre/spl trade/ and waveform calculator capabilities to run.