After almost a decade of research, development of more efficient imprecise computational blocks is still a major concern in imprecise computing domain. There are many instances of the introduced imprecise components of different types, while their main difference is that they propose different precision-cost-performance trade-offs. In this paper, a novel comprehensive model for the imprecise components is introduced, which can be exploited to cover a wide range of precision-cost-performance trade-offs, for different types of imprecise components. The model helps to find the suitable imprecise component based on any desired error criterion. Therefore, the most significant advantage of the proposed model is that it can be simply exploited for design space exploration of different imprecise components to extract the suitable components, with the desired precision-cost-performance trade-off for any specific application. To demonstrate the efficiency of the proposed model, two novel families of Lowest-cost Imprecise Adders (LIAs) and Lowest-cost Imprecise Multipliers (LIMs) are introduced in the paper, which are systematically extracted based on exploration of the design space provided by the proposed model. A wide range of simulation and synthesis results are also presented in the paper to prove the comparable efficiency of the systematically extracted LIA/LIM structures with respect to the most efficient existing human-made imprecise components both individually and in a Multiply-Accumulate application.

Due to considerable effectiveness of the imprecise computing paradigm in hardware implementation of many applications, great attention has been recently paid by many research groups to develop different novel imprecise computational blocks such as adders and multipliers. Traditionally, the imprecise blocks are developed in an application independent manner, just similar to development of a conventional precise block. This article investigates the systematic application oriented development of the imprecise computational blocks which results in more customized components. The main focus is on the development of customized imprecise adder/multiplier for efficient implementation of a general multiply-accumulate (MAC) block as the basic building block of many imprecision tolerant applications including digital signal processing and soft computing. To develop some customized blocks for the MAC, the error behaviors of the suitable imprecise adder and multiplier are first extracted by analyzing the MAC. Based on analysis results, efficient small constant mean-error imprecise adder and multiplier are developed based on a systematic mathematical-logical approach. A wide range of synthesis and simulation results are provided to demonstrate efficiency of custom developed imprecise blocks with respect to some of the best existing imprecise blocks in a general MAC and a real 2D-Convolution application.

Asynchronous serial transceivers have been recently used for data multiplexing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the serial transmission but these links have not been exploited in FPGAs yet. In this paper, we present a new architecture corresponding with a routing algorithm to use the asynchronous wire multiplexing technique in FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (9.37% and 9.03%, respectively) by using the asynchronous wire multiplexing without any performance degradation in cost of a little overhead in area and computation time (2% and 0.84%, respectively)