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Jim Willmore

dblp:190/3360 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › analog and mixed-signal test
analog/RF test
0.212016
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation
hardware verification and test
0.212016
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation › hardware verification and test
test application time reduction
0.212016
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016

Methods — techniques the papers use, named apart from their topics

feature selection · 0.2defect-oriented analysis · 0.2canonical correlation analysis · 0.2
YearPublicationVenuePosition
2016 Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation
abstract
High-cost specification tests of analog/RF devices have become a bottle-neck in reducing the overall cost of high-volume manufacturing (HVM) of systems on chip (SoCs) due to lengthy testing time and expensive test equipment. Especially for fabless semiconductor companies, test time reduction (TTR) is becoming an important priority for developing cost-effective design and manufacturing flow of SoCs. Toward this end, numerous approaches have been developed. In this paper, we point out an important practical issue in implementing feature-selection-based low-cost analog/RF test scheme: in HVM, similar specification tests are often bundled as test suites, which are tested as a whole function by automatic test equipment. Removing some tests in one test suite does not provide much saving on device testing time. We then propose a test-suite-based analog/RF TTR approach using canonical correlation, which aims at identifying correlations between two multivariate sets. We further enhance the incurred test escape by applying a data-driven defect-oriented approach. Experimental results in high-volume industrial data confirm the superiority of the proposed approach over existing methods in terms of both TTR and defective parts per million level.
Ke Huang 0001, Jim Willmore
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3