Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Mark Baranowski

dblp:192/0371 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0009-0840-2761ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 35% Hardware reliability and fault tolerance · 34% Processor architecture and microarchitecture · 26%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
program transformation
0.412020
FailAmp: Relativization Transformation for Soft Error Detection in Structured Address Generation · ACM Trans. Archit. Code Optim. 2020
Processor architecture and microarchitecture
address calculation
0.412020
FailAmp: Relativization Transformation for Soft Error Detection in Structured Address Generation · ACM Trans. Archit. Code Optim. 2020
Hardware reliability and fault tolerance › soft errors
soft error detection
0.412020
FailAmp: Relativization Transformation for Soft Error Detection in Structured Address Generation · ACM Trans. Archit. Code Optim. 2020
Compilers and program optimization › numerical program optimization
floating-point optimization
0.312017
Rigorous floating-point mixed-precision tuning · POPL 2017
Compilers and program optimization › approximate computing › precision tuning
mixed-precision tuning
0.312017
Rigorous floating-point mixed-precision tuning · POPL 2017
Performance modeling and evaluation › numerical algorithms
numerical error analysis
0.312017
Rigorous floating-point mixed-precision tuning · POPL 2017
Performance modeling and evaluation › numerical algorithms › numerical error analysis
round-off error analysis
0.312017
Rigorous floating-point mixed-precision tuning · POPL 2017
Hardware reliability and fault tolerance
fault injection
0.112020
FailAmp: Relativization Transformation for Soft Error Detection in Structured Address Generation · ACM Trans. Archit. Code Optim. 2020
Energy-efficient computing › energy-aware software
energy-aware compilation
0.112017
Rigorous floating-point mixed-precision tuning · POPL 2017

Methods — techniques the papers use, named apart from their topics

fault injection · 0.9SMT solver · 0.9LLVM · 0.9symbolic taylor expansion · 0.6quadratically constrained quadratic program · 0.6interval arithmetic · 0.6
YearPublicationVenuePosition
2025 Equivalence Checking of a libm Port
abstract
Abstract Recent advances in satisfiability modulo theories have brought practical software verification within reach. The advent of the LLVM project presents a common representation which allows verification between programs written in different languages such as C and Rust. New programming languages such as Rust often have less complete standard libraries. In this work, we explore using the SMACK software verifier to check the equivalence of math library routines from the libm library and their translations into native Rust programs.
Mark Baranowski, Zvonimir Rakamaric, Ganesh Gopalakrishnan
TACAS (2)1
2020 FailAmp: Relativization Transformation for Soft Error Detection in Structured Address Generation
abstract
We present FailAmp, a novel LLVM program transformation algorithm that makes programs employing structured index calculations more robust against soft errors. Without FailAmp, an offset error can go undetected; with FailAmp, all subsequent offsets are relativized, building on the faulty one. FailAmp can exploit ISAs such as ARM to further reduce overheads. We verify correctness properties of FailAMP using an SMT solver, and present a thorough evaluation using many high-performance computing benchmarks under a fault injection campaign. FailAmp provides full soft-error detection for address calculation while incurring an average overhead of around 5%.
Ian Briggs, Mark Baranowski, Vishal Chandra Sharma, Sriram Krishnamoorthy, Zvonimir Rakamaric, Ganesh Gopalakrishnan
ACM Trans. Archit. Code Optim.3
2017 Rigorous floating-point mixed-precision tuning
abstract
Virtually all real-valued computations are carried out using floating-point data types and operations. The precision of these data types must be set with the goals of reducing the overall round-off error, but also emphasizing performance improvements. Often, a mixed-precision allocation achieves this optimum; unfortunately, there are no techniques available to compute such allocations and conservatively meet a given error target across all program inputs. In this work, we present a rigorous approach to precision allocation based on formal analysis via Symbolic Taylor Expansions, and error analysis based on interval functions. This approach is implemented in an automated tool called FPTuner that generates and solves a quadratically constrained quadratic program to obtain a precision-annotated version of the given expression. FPTuner automatically introduces all the requisite precision up and down casting operations. It also allows users to flexibly control precision allocation using constraints to cap the number of high precision operators as well as group operators to allocate the same precision to facilitate vectorization. We evaluate FPTuner by tuning several benchmarks and measuring the proportion of lower precision operators allocated as we increase the error threshold. We also measure the reduction in energy consumption resulting from executing mixed-precision tuned code on a real hardware platform. We observe significant energy savings in response to mixed-precision tuning, but also observe situations where unexpected compiler behaviors thwart intended optimizations.
Wei-Fan Chiang, Mark Baranowski, Ian Briggs, Alexey Solovyev, Ganesh Gopalakrishnan, Zvonimir Rakamaric
POPL2