Chips with multiple interconnected dies offer significant advantages over those consisting of only a single monolithic die, driving the rapid adoption of multi-die packages in the market. Die-to-die interconnects are typically realized as large, dense arrays of fine-pitch micro-bumps or hybrid bonds, prone to manufacturing defects like shorts and opens. To address this, typically spare interconnects are included to “repair” defective ones. Repairing is implemented by avoiding the defective interconnects and detouring the functional signals over spare interconnects. This paper proposes a repair scheme for chiplet interconnects with minimal propagation delay for those chiplets that communicate at high speed and do not tolerate too much delay on their interface. Compared to the default UCIe repair scheme, our proposed solution also demonstrates an improved repair rate in case of clustered defects.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Chips with multiple interconnected dies in a package offer significant advantages over those with only a single monolithic die and this is driving the rapid adoption of multi-die packages in the market. In such packages, die-to-die interconnects are typically realized as large, dense arrays of fine-pitch micro-bumps or hybrid bonds, prone to manufacturing defects like shorts and opens. To address this, typically some spare interconnects are included to "repair" defective ones. This paper introduces an Interconnect Repair Language (IRL), based on Google’s Protocol Buffers, to describe all repair provisions. It also presents benefit/cost metrics for evaluation of a repair solution. As benefit metric, we use the spare and repair ratios, while costs are expressed as additional silicon area and propagation delay. We illustrate IRL and the various metrics with a running example from UCIe-Advanced 2.0. Finally, the paper presents a list of potential EDA tools based on the proposed IRL.

This research work addresses various challenges in testing and repairing chiplet-based (2.5D and 3D) multi-die integrated circuits (ICs) as manufacturing shifts toward complex, ultra-dense circuits with large amounts of die-to-die interconnects by micro-bump or hybrid-bump connections and possibly through-silicon vias (TSVs). Conventional interconnect testing methods are limited to detecting hard defects, leading to ineffectiveness, and cover many unrealistic shorts, causing inefficiency. This article introduces E2I-TEST, a method which covers, for a given collection of interconnects, all hard and weak variants of only realistic short, open, and coupling defects. E2I-TEST also prevents aliasing, thus supporting fault diagnosis. While it is predicted that the number of interconnects will rise significantly in the near future, E2I-TEST provides a high-quality interconnect test for which the number of test patterns is constant and no longer dependent on the number of interconnects. To further enhance the yield and reliability of chiplet-based systems, we propose a standardized repair description language for interoperable repair logic of inter-die interconnects, allowing vendors to describe or specify repair structures for automatic verification across various repair logic. We also develop a streamlined, polynomial-time repair algorithm for UCIe designs, minimizing their impact on signal rerouting. Finally, we present micro-bump map optimizations to reduce catastrophic defects and lower the spare interconnect usage. This work provides a comprehensive testing and repair framework, enhancing defect resilience and yield in future ICs.

Chiplet-based (2.5-D and 3-D) multidie packages typically feature numerous die-to-die interconnects using micro-bump connections and possibly through-silicon vias or interposer wires, which are prone to manufacturing defects, such as shorts and opens, in both hard and weak (resistive) variants. Traditional I-ATPG methods only cover hard defects and scale with the logarithm of the number of interconnects. Despite being considered efficient, they cover shorts between all interconnects, including those for which shorts are unrealistic given their relative layout positions. This article proposes E2I-TEST, which covers all hard and weak variants of open defects and of only the shorts and coupling defects between physically adjacent interconnects for both 3-D and 2.5-D chips, while preventing aliasing during fault diagnosis. This article further improves E2I-TEST to prevent ground bounce, avoiding undesired voltage fluctuations during test mode. While the number of interconnects is expected to rise significantly, E2I-TEST offers a high-quality interconnect test, while maintaining a constant number of test patterns.

IEEE Std P3405 is a new standardization activity under the umbrella of TTTC’s Test Technology Standardization Committee (TTSC). In 2023, a Study Group formulated a Project Authorization Request (PAR), which was approved and since December 1, 2023, the P3405 Working Group is active under elected chair Sreejit Chakravarty. This standardization activity focuses exclusively on the test and repair of chiplets’ inter-die interconnects. In the PAR, the scope of the activity is described as follows. "Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair. The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (prepackaging), Packagers’, and End Users’ test and repair objectives." In this special session, a handful prominent members of the Working Group express their personal views on the outcome of the standardization work. The views expressed are from the authors alone and do not necessarily align with the view of the IEEE Std P3405 Working Group.

The success of chiplet-based design critically depends on standards, especially those for die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard, showing promising potential in its field. Among other things, UCIe standardizes the micro-bump map. It incorporates several spare interconnects able to "repair" defective interconnects. We outline a very efficient, aliasing-free test generation method for all hard and weak short and open manufacturing defects on die-to-die interconnects that uses just 16 test patterns, irrespective of the number of interconnects. We also propose to improve repairability of the UCIe interconnects through reorganizations of the micro-bump map that eliminate the risk for non-repairable (‘catastrophic’) defects and minimizes the usage of spare interconnects. The micro-bump map reorganizations are not backwards compatible and hence, since UCIe is still in its early stages of actual usage, it would be best to incorporate this improvement in the standard as soon as possible.

From the Project Authorization Request (PAR) of IEEE Std P3405: “Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair. The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (pre-packaging), Packagers’, and End Users’ test and repair objectives.”

Chiplet-based multi-die packages (a.k.a. 2.5D- and 3D-ICs) implement large amounts of inter-die interconnects with micro-bumps. To achieve uniform heights, these micro-bumps are typically placed in large rectangular or hexagonal arrays. These interconnects are subject to manufacturing defects. Traditional interconnect automatic test pattern generation (I-ATPG) methods, such as the True/Complement Algorithm [1], focus on hard open and short defects with test pattern count 2 × ⌈log2(k)⌉ for k interconnects. However, the traditional I-ATPG methods indiscriminately cover short defects between all pairs of interconnects, including those for which shorts are unrealistic given their relative layout positions. In this paper we propose an effective and efficient interconnect test (E2ITEST). The proposed method improves the test effectiveness by covering both hard and weak variants of open and short defects. It improves the test efficiency by considering only shorts between adjacent interconnects. Because of this, it requires 8 × ⌈log2(4)⌉ = 16 test patterns, thereby decoupling it from the dependency on k, which is large already today and only expected to grow.

Chiplet-based multi-die packages implement large numbers of inter-die interconnect bundles clustered in large micro-bump islands. These micro-bumps can be subject to manufacturing defects. The most common defect types are shorts and opens. Traditional interconnect automatic test pattern generation (I-ATPG) algorithms detect, for a given collection of interconnects, all shorts between any pair of interconnects, all open interconnects, and exclude any aliasing, independent from the interconnects’ layout positions. Exploiting knowledge of their relative layout positions, we derive a new, improved I-ATPG algorithm. For a user-defined and scalable definition of realistic shorts, the new I-ATPG approach (1) increases the defect coverage significantly (in an example case, between 18% and 67%) by including realistic inter-bundle shorts between micro-bumps from adjacent bundles, and (2) reduces the overall test pattern count (and hence, the resulting test time) by 33% by providing test patterns for realistic shorts only.

This paper introduces a low-power 90nm CMOS binary weight spiking neural network (BW-SNN) ASIC for real-time image classification. The chip maximizes data reuse through systolic arrays that house the entire 5-layer BW-SNN, requiring a minimum off-chip bandwidth for data access. The chip achieves 97.57% accuracy for real-time bottled-drink recognition, consuming only 0.62uJ per inference. For comparison purpose, it achieves 98.73% accuracy for MNIST hand-written character recognition, consuming only 0.59uJ per inference. The bottled-drink recognition is demonstrated at 300 fps that is well enough for many other real-time applications. The peak efficiency point is 103.14TOPS/W at a voltage of 0.6V, which outperforms other designs so far as we know. By normalizing to the 28nm technology node, the proposed ASIC is about 5× more efficient and 7× lower hardware cost as compared with the state-of-the-art designs.

With the advent of highly complex and dense modern CMOS circuits, defects caused by parametric and process variations, e.g., are more and more difficult to detect. Many hard-to-detect defects not sensitized through the critical paths can easily escape from the conventional testing methods. In order to reduce the product defect level, we introduce the notion of quorum sensing (QS) to circuit testing (sensing) for improving the quality and reliability. The proposed thermal quorum sensing (TQS) mechanism triggers a thermal chain reaction to expose the subtle variations in the circuit due to small defects, which can be observed by the common cell population behavior. A model is introduced to charactize the feature of TQS on circuit. The simualtion result verified by the ISCAS s9234 benchmark with 45nm CMOS standard cell library shows when the number of small defects injected is more than 489, the difference in total current will be higher than 2.08mA. It can discover the subtle faults compared with other state-of-the-art or traditional testing methods.

In this paper, we propose an efficient test flow for Cell-Aware Test (CAT) to drastically reduce the time for CAT-enhanced test generation at the cell level. In CAT, the detail transistor-level circuit simulation is used to find appropriate test patterns and it has been considered as very time consuming. To solve this problem, first, we exploit Switch-Level ATPG (SL-ATPG) and experimentally show that it can efficiently generate test patterns in the CAT flow. Second, based on layout-oriented defect generation method, we propose an algorithm to automatically inject those defects into the switching network used in SL-ATPG, for cells in the library. Third, note that the traditional ATPG is primarily based on the stuck-at-fault and transition-fault models, it is difficult to find small-delay faults. However, the same defects are likely to be detected by observing the short-circuit current, so we propose current-based checks for a pattern generation method which are able to detect the existence of a short-circuit path. Finally, we compare the simulation time of detailed circuit simulation and of SL-ATPG in CAT. The experiment is based on a commercial 180nm CMOS standard cell library. Moreover, it shows that SL-ATPG method can successfully reduce the simulation time by about 403X.

This paper proposes methods to drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models. By exploiting low-power properties of common CMOS designs, most defects in the transistor-level netlist containing parasitics can be represented by just two canonical fault classes. Via simple circuit analysis, we show that faulty behaviors are completely predictable as the defect resistance parameter value varies from zero to infinity, thus eliminating the need for circuit simulation at multiple parameter values. The two canonical fault classes can be modeled by transistor switch stuck-open and stuck-closed faults. Rather than enumerating the full combination cell input patterns to search for defect detection conditions by analog fault simulation, switch-level test generation can obtain those input conditions directly, thereby reducing significantly the role of analog simulation to that of ranking conditions in terms of detection effectiveness.