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Kishore K. Chidella

dblp:193/3086 · also Kishore Konda Chidella · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
0000-0002-5002-3169ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 36% Processor architecture and microarchitecture · 28% Interconnection networks and networks-on-chip · 28%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
chip multiprocessor
0.312017
An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency · IEEE Trans. Parallel Distributed Syst. 2017
Memory systems › cache coherence
directory-based coherence
0.312017
An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency · IEEE Trans. Parallel Distributed Syst. 2017
Interconnection networks and networks-on-chip › network-on-chip design
wireless network-on-chip
0.312017
An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency · IEEE Trans. Parallel Distributed Syst. 2017
Memory systems
cache coherence
0.112017
An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency · IEEE Trans. Parallel Distributed Syst. 2017

Methods — techniques the papers use, named apart from their topics

simulation · 0.3
YearPublicationVenuePosition
2017 An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency
abstract
Multicore architectures suffer from high core-to-core communication latency primarily due to the cache's dynamic behavior. Studies suggest that a directory-approach can be helpful to reduce communication latency by storing the cached block information. Recent studies also indicate that a wireless router has potential to help decrease communication latency in multicore architectures. In this work, we propose a directory based multicore architecture with wireless routers to minimize communication latency. We simulate systems with mesh (used in the Standford Directory Architecture for SHared memory (DASH) architecture), wireless network-on-chip (WNoC), and the proposed directory based architecture with wireless routers. According to the experimental results, our proposed architecture outperforms the WNoC and the mesh architectures. It is observed that the proposed architecture helps decrease the communication delay by up to 15.71 percent and the total power consumption by up to 67.58 percent when compared with the mesh architecture. Similarly, the proposed architecture helps decrease the communication delay by up to 10.00 percent and the total power consumption by upto 58.10 percent when compared with the WNoC architecture. This is due to the fact that the proposed directory based mechanism helps reduce the number of core-to-core communication and the wireless routers help reduce the total number of hops.
Abu Asaduzzaman, Kishore K. Chidella, Divya Vardha
IEEE Trans. Parallel Distributed Syst.2