Light detection and ranging (Lidar) is usually enabled by Single-Photon Avalanche Detector (SPAD) sensors which may be falsely triggered by ambient light. Coincidence detection can suppress the ambient light at the cost of the lateral resolution. A$64\times 64$SPAD image sensor with coincidence detection is proposed for Lidar. A main-sub time-to-digital converter (TDC), in which the main TDC is used for timestamping the coincidence window and the sub-TDC is used for timestamping the event within the coincidence window, is proposed to avoid the loss of the lateral resolution at a small power cost. A delay-locked loop (DLL) is adopted to generate an analog voltage for maintaining the length of the coincidence window against process-voltage-temperature (PVT) variations. A TDC code correction circuit is proposed to reduce the probability of TDC inter-segment errors to 0.7%. The SPAD image sensor is based on the 3D integration of a SPAD array with a ROIC. The ROIC chip is fabricated in a$0.18\mu $m CMOS process. Driven by a 250 MHz multi-phase clock and a 100 MHz data readout clock, the chip achieves a maximum frame rate of 35.7 kframe/s, a timing resolution of 0.5 ns, and a timing range of$2\mu $s. The typical average power consumption of the ROIC is 135.5 mW (@21.7 kframes/s). The measured differential nonlinearity (DNL) ranges from -0.74 to +0.82 least significant bit (LSB), and the integral nonlinearity (INL) ranges from -0.95 to +0.95 LSB.

More and more Non-Volatile Memories (NVM) have been widely applied to various embedded systems to build the heterogeneous memory architecture. However, the write-endurance of NVM remains a great challenge. Hence, we should take full consideration of the write-endurance of NVM when allocating data on heterogeneous memory architecture. There is an observation that, for most real workloads, about 10% of data account for 90% write operations. This brings us an opportunity to reduce the write wear of NVM through carefully allocating write-intensive data. In this paper, we explore the problem that how to find a balance between the system cost and write-endurance of NVM for data allocation on heterogeneous memory architecture. We propose a write-aware data allocation algorithm, WADA. WADA can not only greatly reduce the write wear of NVM, but also guarantee the near-optimal system cost. We also propose an integer linear programming (ILP) model to generate an optimal data allocation, which can obtain the minimum cost. The result of ILP can be used as a standard to evaluate the efficiency of other algorithms. Experiments show that WADA outperforms all the other algorithms on both system cost and write wear of NVM. Compared to previous algorithms, WADA can reduce up to 47.77% system cost and 60.89% write wear of NVM. Compared to ILP, WADA can achieve the near-optimal system cost within just 2% difference.