Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a design under test (DUT) reacts to different error-injection methodologies is essential for verification engineers to design dependable universal verification methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error-injection techniques when used with networks-on-chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error-injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: 1) a base router and 2) Daniel router. Base router is a simple case study to prove proposed schemes, whereas Daniel router is a complex reconfigurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of this paper is to integrate a full UVM environment with various verification approaches. Target approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an N × N 2-D network composed of base routers or Daniel routers.

With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 μW/MHz power consumption.

Flexibility either in buffering or routing is a very promising solution for NoC congestion problem. In this paper, a new 3D router with flexible architecture is introduced and validated for 3D NoCs. In fact, the Flexible router architecture introduced in literature would be deadlock prone if it is incorporated in a 3D NoC domain. We successfully design the new buffering constraints and extensively evaluate its performance under various traffic scenarios using real benchmark applications. We show the great enhancement of the new candidate router architecture in comparison to the conventional 3D NoC router architecture. Finally, we show that this enhancement in performance comes at a very low impact in power and area; especially for large NoC sizes.