Demo Data from VLDB 2026 / reviewers in the wild / expert
César-Alejandro Hernández-Calderón
dblp:195/1946
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Performance modeling and evaluation · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › simulation
architectural simulation |
0.4 | 1 | 2020 | A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures · ACM Trans. Archit. Code Optim. 2020 |
Performance modeling and evaluation
benchmarking |
0.4 | 1 | 2020 | A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures · ACM Trans. Archit. Code Optim. 2020 |
Processor architecture and microarchitecture › instruction set architecture › vector extension
RISC-V vector extension |
0.4 | 1 | 2020 | A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures · ACM Trans. Archit. Code Optim. 2020 |
Processor architecture and microarchitecture
vector processor |
0.4 | 1 | 2020 | A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures · ACM Trans. Archit. Code Optim. 2020 |
Methods — techniques the papers use, named apart from their topics
parameterizable vector model · 0.4gem5 simulation · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector ArchitecturesabstractVector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that includes a flexible and customizable vector architecture model. In consequence, researchers have to develop their own simulation platform to test their ideas, which consume much research time. However, once the base simulator platform is developed, another question is the following: Which applications should be tested to perform the experiments? The lack of Vectorized Benchmark Suites is another limitation. To face these problems, this work presents a set of tools for designing and evaluating vector architectures. First, the gem5 simulator was extended to support the execution of RISC-V Vector instructions by adding a parameterizable Vector Architecture model for designers to evaluate different approaches according to the target they pursue. Second, a novel Vectorized Benchmark Suite is presented: a collection composed of seven data-parallel applications from different domains that can be classified according to the modules that are stressed in the vector architecture. Finally, a study of the Vectorized Benchmark Suite executing on the gem5-based Vector Architecture model is highlighted. This suite is the first in its category that covers the different possible usage scenarios that may occur within different vector architecture designs such as embedded systems, mainly focused on short vectors, or High-Performance-Computing (HPC), usually designed for large vectors. Cristóbal Ramírez, César-Alejandro Hernández-Calderón, Oscar Palomar, Osman S. Unsal, Marco A. Ramírez 0001, Adrián Cristal |
ACM Trans. Archit. Code Optim. | 2 |