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Hsueh-Chun Fu

dblp:195/4164 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Hardware accelerators and domain-specific architectures · 23%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management
virtual memory
0.312018
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures · DAC 2018
Hardware accelerators and domain-specific architectures › accelerator architecture
accelerator-rich architecture
0.112018
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures · DAC 2018

Methods — techniques the papers use, named apart from their topics

scratchpad memory · 0.3active forwarding · 0.3
YearPublicationVenuePosition
2018 Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures
abstract
Accelerator-rich architectures employ IOMMUs to support unified virtual address, but researches show that they fail to meet the performance and energy requirements of accelerators. Instead of optimizing the speed/energy of IOMMU address translation, this work tackles the issue from a new perspective, eliminating the need for translation with an active forwarding (AF) mechanism that forwards input data of accelerators directly from the CPU cache to the scratchpad memory of the accelerator. Results show that on average, AF can provide 8% performance improvement compared to the state-of-the-art mechanism, hostPageWalk, and reduce 22.1% accelerator power.
Hsueh-Chun Fu, Po-Han Wang 0001, Chia-Lin Yang
DAC1
2017 Enabling fast preemption via Dual-Kernel support on GPUs
abstract
To consider QoS for resource-limited mobile systems, we introduce a fast preemption mechanism on GPUs. First, we involve a dual-kernel execution model to support fine-grained preemption, and a resource allocation policy to avoid resource fragmentation problem. Second, we propose a preemption victim selection scheme to reduce the throughput overhead while satisfying a required preemption latency. Evaluations show that we can reach very close to the ideal preemption scheme within 2% difference in terms of deadline violations. Furthermore, on average we improve GPU resource utilization by 2.93× over prior technique during preemption.
Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang 0001, Chia-Lin Yang
ASP-DAC3