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Tianqi Mao 0003

dblp:195/5435-3 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0005-6108-859XORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 43% GPUs and heterogeneous computing · 27% Processor architecture and microarchitecture · 16%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture
1.012026
SMEStencil: Optimizing High-Order Stencils on ARM Multicore Using SME Unit · IEEE Trans. Parallel Distributed Syst. 2026
High-performance computing
stencil computation
1.012026
SMEStencil: Optimizing High-Order Stencils on ARM Multicore Using SME Unit · IEEE Trans. Parallel Distributed Syst. 2026
High-performance computing › scientific computing systems
cryo-EM 3D reconstruction
0.912025
T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction · SC 2025
GPUs and heterogeneous computing
GPU computing
0.912025
T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction · SC 2025
High-performance computing
scientific computing systems
0.912025
T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction · SC 2025
GPUs and heterogeneous computing › GPU computing
tensor cores
0.912025
T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction · SC 2025
Memory systems
non-uniform memory access
0.312026
SMEStencil: Optimizing High-Order Stencils on ARM Multicore Using SME Unit · IEEE Trans. Parallel Distributed Syst. 2026
Parallel and multicore computing › parallel programming models
task parallelism
0.312025
T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction · SC 2025

Methods — techniques the papers use, named apart from their topics

vectorization · 1.0DMA · 1.0three-phase GPU memory management · 0.9thread-block data reuse · 0.9pipelining · 0.9
YearPublicationVenuePosition
2026 SMEStencil: Optimizing High-Order Stencils on ARM Multicore Using SME Unit
abstract
Matrix-accelerated stencil computation is a hot research topic, yet its application to 3 dimensional (3D) high-order stencils and HPC remains underexplored. With the emergence of Scalable Matrix Extension(SME) on ARMv9-A CPU, we analyze SME-based accelerating strategies and tailor an optimal approach for 3D high-order stencils. We introduce algorithmic optimizations based on Scalable Vector Extension(SVE) and SME unit to address strided memory accesses, alignment conflicts, and redundant accesses. We propose memory optimizations to boost on-package memory efficiency, and a novel multi-thread parallelism paradigm to overcome data-sharing challenges caused by the absence of shared data caches. SMEStencil sustains consistently high hardware utilization across diverse stencil shapes and dimensions. Our DMA-based inter-NUMA communication further mitigates NUMA effects and MPI limitations in hybrid parallelism. Combining all the innovations, SMEStencil outperforms state-of-the-art libraries on Nividia A100 GPGPU by up to 2.1× . Moreover, the performance improvements enabled by our optimizations translate directly to real-world HPC applications and enable Reverse Time Migration(RTM) real-world applications to yield 1.8x speedup versus highly-optimized Nvidia A100 GPGPU version.
Tianqi Mao 0003, Lin Gan 0008, Wubing Wan, Jiayu Fu, Lanke He, Zekun Yin, Wei Xue 0003, Guangwen Yang 0002
IEEE Trans. Parallel Distributed Syst.2
2025 T2-RELION: Task Parallelism, Tensor Core Accelerated RELION for Cryo-EM 3D Reconstruction
abstract
Cryo-electron microscopy (cryo-EM) is a key technique for structural biology, but its computational efficiency, particularly during 3D reconstruction, remains a bottleneck. We introduce T2-RELION, a highly optimized version of RELION for cryo-EM 3D reconstruction on CPU-GPU platforms. RELION is a widely used open-source package in the cryo-EM community. We identify and resolve key inefficiencies in RELION’s parallelization strategy and memory management by proposing task parallelism and a three-phase GPU memory management strategy. Furthermore, we leverage Tensor Cores to accelerate the hot-spot kernel for difference calculation, employing an advanced pipelining strategy to hide latency and enable thread-block-level data reuse. On a quad-A100 GPU machine, performance evaluations demonstrate that T2-RELION outperforms RELION 4.0. For the hot-spot kernel, our optimizations achieve 1.90-23.7 times speedup. For the whole application using CNG and Trpv1 datasets, we observe 3.86 times and 2.68 times speedups, respectively.
Jiayu Fu, Jingle Xu, Lin Gan 0001, Tianqi Mao 0003, Zirong Shen, Xiaohui Duan, Wei Xue 0003, Guangwen Yang 0002
SC4