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Allen Deng

dblp:195/6463 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › transactional memory
hardware transactional memory
0.312017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017
Parallel and multicore computing › transactional memory
hybrid transactional memory
0.312017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017
Parallel and multicore computing
transactional memory
0.312017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support · PPoPP 2017

Methods — techniques the papers use, named apart from their topics

software fall-back path · 0.3
YearPublicationVenuePosition
2017 POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support
abstract
In this work, we introduce and experimentally evaluate a new hybrid software-hardware Transactional Memory prototype based on Intel's Haswell TSX architecture. Our prototype extends the applicability of the existing hardware support for TM by interposing a hybrid fall-back layer before the sequential, big-lock fall-back path, used by standard TSX-supported solutions in order to guarantee progress. In our experimental evaluation we use SynQuake, a realistic game benchmark modeled after Quake. Our results show that our hybrid transactional system,which we call HythTM, is able to reduce the number of transactions that go to the sequential software layer, hence avoiding hardware transaction aborts and loss of parallelism. HythTM optimizes application throughput and scalability up to 5.05x, when compared to the hardware TM with sequential fall-back path.
Arnamoy Bhattacharyya, Mike Dai Wang, Mihai Burcea, Allen Deng, Sai Varikooty, Shafaaf Hossain, Cristiana Amza
PPoPP5