Non-terrestrial networks (NTNs) are becoming an attractive approach in 6G era to provide ubiquitous connectivity to everywhere. NTN is expected to bring opportunities for cost-effective coverage extension from the sky using satellites and aircraft as flying base stations. However, NTN also brings challenges in providing stable communication due to changes in network topology and communication environment over time, which needs continuous path selection. This paper proposes a path selection method that selects paths based on a predicted path computation rule for each time using a graph neural network (GNN) model that takes graphs with heterogeneous nodes as input. An NTN is transformed into graphs with heterogeneous nodes, where both network nodes and links become heterogeneous nodes in the transformed graph, to enable taking both features of network nodes and links as explicit input to GNN models. Evaluation results show that the proposed method outperforms existing routing methods in terms of packet delivery ratio of multiple traffic flows with different pairs of source and destination. The proposed method also outperforms flow-dependent models even for unseen traffic flows in training, which demonstrates that representing NTN by graphs with heterogeneous nodes and using GNN models enable flow-independent path selection.

Future carrier networks will need to aggregate traffic from widely distributed sensor nodes while meeting stringent service requirements in industrial and logistics applications. As these networks scale, ensuring deterministic latency and cost efficiency becomes increasingly critical. Technologies with optical transmission and aggregation capabilities, such as Passive Optical Networks (PONs) with switching functions, offer cost-effective solutions. However, the queuing delays caused by multi-stage traffic aggregation for large-scale data collection must be accurately estimated to meet performance requirements. Traditional machine learning approaches for the queuing delay estimation often rely heavily on large labeled datasets, which are expensive and impractical to collect in large-scale environments. To address these limitations, this study proposes a Queue-Informed Neural Network (QINN) that incorporates governing equations derived from queuing theory into the neural network training process. By embedding queuing principles into the learning model, the proposed QINN improves the accuracy of queuing delay estimations without requiring extensive datasets. Application of the proposed QINN model to simulation data under different aggregation scenarios, such as PONs combined with an Ethernet switch, demonstrates improved the accuracy of queue delay estimation. These results highlight the potential of integrating governing equations based on queuing theory to improve queuing delay estimation in aggregation networks.

Future carrier networks for 6G are expected to verify performance across heterogeneous networks integrating multiple technologies. This integration requires effective verification of network performance under unpredictable conditions. In response, a node modeling method has been proposed for digitally evaluating the performance of actual network nodes. However, creating accurate node models is challenging due to the high cost and difficulty of collecting extensive real-world data under various environmental conditions. Therefore, the objective of this study is to improve the performance of actual network nodes using limited real-world datasets. We investigate the potential of natural language processing technologies to improve the accuracy of router performance estimation. In this paper, we propose a Feature Name Decoration (FND) method using Large Language Models (LLMs) to predict actual router metrics. The FND can help clarify the relationships between specific features, such as router settings and traffic conditions, and their impact on router metrics. The results show that the proposed FND improves the estimation accuracy of actual router performance metrics, including throughput, packet loss rate, and packet delay.

Future carrier networks for 6G are expected to verify the performance across heterogeneous networks integrating multiple technologies. This integration requires effective verification of network performance under unpredictable conditions. In response, a node modeling method has been proposed for digitally evaluating the performance of actual network nodes. However, creating the node model is challenging due to the high cost and difficulty of collecting extensive real-world data under various environmental conditions to train the node model. Alternatively, fine-tuning the model with data from different data-rich domains could increase the operational cost due to the selection of utilized data and the decisions on which parameters to retain. Therefore, the objective of this study is to improve the performance of actual network nodes using limited real-world data without complex fine-tuning. We explore how natural language processing enhances router performance estimation. Here, we propose an attentive Retrieval-Augmented Generation (RAG) method with Large Language Models (LLMs) for estimating actual router performance by augmenting real-world data with the most relevant simulation data. The results show that the proposed attentive RAG with the LLM improves the estimation accuracy of actual router performance metrics: throughput, packet loss rate, and packet delay.

Future carrier networks for 6G are expected to guarantee the performance across heterogeneous networks that integrate multiple technologies. This integration requires the effective verification of network performance under unpredictable conditions. To address this, the network digital replica (NDR) has been proposed to evaluate the performance of actual network equipment digitally. However, a major challenge of the NDR is the difficulty and expense of acquiring extensive real-world datasets for various traffic patterns, which is necessary for training actual network node models. This paper proposes a meta learner-based transfer learning to infer actual router metrics based on the model using network simulation data. The proposed method aims to build a model of actual router metrics based on limited real-world datasets by supplementing it with different ranges and types of simulation data. To address the differences in these datasets, the proposed method utilizes Neural Processes as a meta-learner combined with Partial Least Squares analysis to capture and bridge the representation for packet multiplexing tasks between simulation and real-world datasets for transfer learning. The results show that the proposed method improves the inference accuracy of actual router metrics; throughput, packet loss rate, and packet delay.

Non-terrestrial networks (NTN) are becoming an attractive approach in beyond 5G/6G era to provide ubiquitous connectivity to everywhere, including uncovered or underserved areas. NTN enables efficient coverage of large areas from the sky by using satellites and aircraft as flying network nodes such as base stations and routers. In contrast, the node mobility of NTN introduces dynamic changes in the network topology, requiring continuous updates of the control plane, such as routing, to ensure stable communications in terms of packet delivery and latency. In addition, dynamic changes in the communication environment, such as weather, cause link quality and availability to fluctuate. As a result, existing path selection approaches may result in the selection of poor-quality paths even though they involve frequent control message flooding for topology discovery and path finding. This paper proposes a centralized path selection method in NTN using multiple path selection rules adaptively based on link information to increase packet delivery rate with fewer control messages. The path selection rule at each time is predicted by a machine learning (ML) model based on the link information. The rule prediction model is trained by training scenarios of an NTN with different parameters. Simulation results show that the proposed method outperforms the existing methods in terms of packet delivery rate and maximum latency with less than 1 % of control messages. The results also show that each of the multiple path selection rules in the proposed method contributes to increasing the packet delivery rate.

Future network infrastructures will need to provide network services safely and rapidly under complex conditions that include accommodating many devices and multiple access lines such as 5G / 6G supported by multiple carriers. Further-more, future carrier networks will support network disaggre-gation technologies to leverage best-of-breed technology from different suppliers in accordance with the service requirements. Therefore, the efficiency of the verification needs to be improved for the combinations of a large amount of various network equipment and components constituting the network infrastructure to ensure network quality and reliability for unknown network conditions. The issue focused on this study is how to improve the prediction accuracy for the metrics of black-boxed network nodes when only the network node settings and traffic conditions are known as the external conditions. To address this, here, we propose machine learning based node modeling to improve the accuracy of predicted network node metrics by recursively adding other predicted metrics to the training datasets step by step in accordance with the feature importance. Experimental results show that the coefficient of determination (R2) of router metrics the throughput, the packet loss, and the packet delays, could be improved by using the training datasets including router settings and other predicted router metrics.

Future network infrastructures will need to provide network services safely and rapidly under complex conditions that include accommodating many devices and multiple access lines such as 5G / 6G supported by multiple carriers. For this reason, the efficiency of the pre-verification needs to be improved for a large number of various devices to ensure safety and reliability. Furthermore, future carrier networks will support network disaggregation technologies to leverage best-of-breed technology from different suppliers in accordance with service requirements. Therefore, it is necessary to verify combinations of a large number of devices and the components constituting the network infrastructure to achieve optimal settings. In this paper, we propose the concept of network digital replica and a method of network node modeling to predict the performance of network nodes using neural-network-based machine learning. A network digital replica, which is a copy of a physical network, can be created in a digital domain not only to classify the specifications of network nodes but also to verify the performance for network devices digitally. We evaluate the effectiveness of the proposed method, which predicts the throughput and processing delays of actual routers on the basis of the sets of learning data including router settings and traffic conditions.

Packet processing tasks in network functions require high-performance memory systems to understand the packet information, update the packet content, and search the databases. While network virtualization is expected to bring flexible and adaptive network with reduced cost by using commercial off-the-shelf (COTS) hardware and programmable data plane technology, network function performance suffers from the poor memory systems in COTS computers and lack of scalability in programmable hardware devices. This paper proposes a memory network architecture for packet processing based on memory-centric, disaggregated computing. Unlike processor-centric architecture in today’s COTS computers, the memory network consists of multiple memory devices, where processing for the incoming packets is completed. The proposed architecture reduces packet processing latency by eliminating communication between the processor devices and the memory devices. Also, the proposed architecture provides scalability of hardware resources by dynamic memory device allocation depending on the complexity of the network function, memory-intensiveness of packet processing, and traffic load. The numerical results show that the proposed architecture reduces accumulated latency for memory accesses and increases throughput compared to the conventional, processor-centric architectures, where every memory access requires communication between the processor devices and the memory devices. The proposed architecture also reduces latency and increases throughput by allocating additional memory devices to memory-intensive tasks.

Packet processing tasks in network functions issue memory requests to understand the packet information, update the packet content, and search the databases, which requires high-performance memory systems. While network functions virtualization (NFV) is expected to reduce the cost of network infrastructure by replacing dedicated network equipment with commercial off-the-shelf (COTS) hardware and virtual network functions (VNFs), VNF performance suffers from the poor memory systems that lack function-dedicated memories and memory parallelism in COTS servers. While several works presented parallel memories for packet processing based on 3 dimensional (3D)-stacked dynamic random access memories (DRAMs), data transfer latency between the processors and memories are not considered. Although there are processing-in-memory (PIM) architectures that offload a part of processing in memories to reduce data transfers, the majority of processing is still in the processors, which requires data transfers for multiple packet processing tasks. This paper proposes a memory network architecture using 3D-stacked DRAMs to increase throughput and reduce accumulated latency when there are multiple packet processing tasks. Packets that enter the memory network receive packet processing at each 3D-stacked DRAM without data transfers between the processors and memories. The evaluation results show that the proposed architecture increases throughput and reduces accumulated latency for memory accesses and data transfers when there are multiple packet processing tasks, compared to the conventional architecture with 3D-stacked DRAM-based parallel memory, where every memory access requires data transfers.

The performance of packet processing applications is dependent on memory accesses speed of network systems. Table lookup requires fast memory accesses and is one of the most common processes in various packet processing applications, which can be a dominant performance bottleneck. Therefore, in Network Function Virtualization (NFV)-aware environment, on-chip fast cache memories of a CPU of general-purpose hardware become critical to achieve high performance packet processing over tens of Gbps. In addition, multiple types of applications and complex applications are executed in the same system simultaneously in carrier network systems, which require the capacity of cache memories as well. In this paper, we propose a packet processing architecture that utilizes interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices as off-chip Last Level Cache (LLC) in addition to several levels of dedicated cache memories of each CPU core. Entries of a lookup table are distributed in every bank and vaults to utilize both bank interleaving and vault-level memory access parallelism. Frequently accessed entries in 3D-stacked DRAM are also cached in dedicated on-chip cache memories of each CPU core. The evaluation results show that the proposed architecture reduces the memory access latency by 57 % and increases the throughput by 100 % with reducing blocking probability about 10 % compared to the conventional architecture with common on-chip LLC. These results indicate that 3D-stacked DRAM can be practical as off-chip LLC in parallel packet processing running on multiple CPU cores simultaneously.

Emergence of new network services such as Internet of Things (IoT) and edge computing accelerates the increase of traffic volume, the number of connected devices and the diversity of communication. Next generation carrier network infrastructure should be much more scalable and adaptive to rapid increase and divergence of network demand with much lower cost. More virtualization-aware, flexible and inexpensive system based on general-purpose hardware is necessary to transform traditional carrier network into more adaptive, next generation network. In this paper, we propose a carrier-scale packet processing system which utilizes 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) device. The proposed system augments memory access concurrency by leveraging vault-level parallelism and bank interleaving of 3D-stacked DRAM. The system uses hash-function-based distributor of memory requests to each set of vault and bank which accommodates a portion of original carrier-scale huge tables. We introduce an analytical model for the system. The evaluation result shows that our proposed system can achieve more than 100 Gbps in carrier-scale packet processing where main memory accesses are inevitable since tiny CPU cache memory is insufficient to accommodate huge tables. Our analytical model is independent of specification of a particular device, which can be applied to any DRAM systems.