This paper presents a broadband low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) in 0.15-μm GaN-on-SiC technology. The LNA circuit is designed into a three-stage topology with three coupled-line structures. The first coupled-line structure is designed at the first stage for wideband input impedance matching and noise cancellation, while the second one is employed at the inter-stage to realize thegm-boost for gain enhancement. Then, the last coupled-line structure forms a positive feedback signal paths from the drain to the gate of the output-stage transistor, which compensates the gain degradation at the high frequency band. With these three coupled-line structures, flat gain performance and low noise figure are achieved in a broadband frequency range. For demonstration, the LNA MMIC is fabricated. The measured results show a maximum gain of 22.6 dB at 27.6 GHz and a 3-dB bandwidth of 22.6 GHz from 7.2 to 29.8 GHz. The in-band noise figure is measured as 1.35-2.67 dB, while the output 1dB gain compression point (OP1dB) and output third-order intercept point (OIP3) are 20.9 dBm and 34.8 dBm at 28.5 GHz, respectively. The fabricated LNA has a compact die area of 2.64 mm2including all test pads.

In this paper, we propose a compact wideband on-chip millimeter-wave (mm-wave) reconfigurable wideband filtering switch in 28-nm bulk CMOS technology. A dual-mode LC resonator loaded with transistors is used to achieve wideband filtering responses with a transmission zero at the lower frequency band. The resonant frequency of the resonator and the location of the transmission zero can be conveniently tuned to reconfigure the passband and stopband frequencies by turning on and off the transistor. Moreover, the passband can also be switched on and off, enabling the single-pole single-throw filtering switch circuit function. In this way, the proposed mm-wave reconfigurable filtering switch is applicable to the integrated sensing and communication (ISAC) system, where image rejection in communication operation and a wide bandwidth (or high resolution) in sensing operation are both required. Furthermore, to meet the applications in the ISAC systems with different architectures, extension designs of the proposed reconfigurable filtering switch with the impedance conversion function, high-order responses, balanced-to-unbalanced transition, and differential input/output ports are presented in detailed. For demonstration, the wideband reconfigurable filtering switch has been fabricated. The core circuit has a very compact size of$0.205\times 0.140$mm2. Experimental results show that the passband can be reconfigured between 20-55 GHz and 37-44 GHz, with a rejection >17 dB for sensing operation and >12 dB image-band rejection for communication operation, respectively. High off-state isolation of better than 24.8 dB is also achieved.

This paper presents a three-stage wideband LNA with gain switching technique designed for 5G millimeter-wave applications operating at 23.6-46.5 GHz. By deriving an analytical equation of input impedance and noise matching, a two-pole matching network based on ladder transformer is introduced. The coupling between the transformers can be used to control the two poles of S11 and simultaneously match the source impedance to the optimized noise impedance, achieving broadband input matching and low noise figure (NF). A 24 dB gain tuning range with 6 dB per step has been designed to accommodate different input power level for automatic gain control (AGC). The gain control is implemented with current slicing at the 2nd and 3rd stages, which can keep input/output impedance nearly constant during gain switching. The proposed wideband LNA has been fabricated in 28-nm bulk CMOS process with a chip size of only 0.13 mm2. Measured results show a peak gain of 23 dB within a 3-dB bandwidth from 23.6 to 46.5 GHz, with S11 better than −10 dB over the bandwidth. The measured NF is 2.2 – 3.7 dB with an average of 3 dB. The input 1 dB gain compression point (IP1dB) ranges from −27 to −23.8 dBm throughout the gain bandwidth. Moreover, the measured gain can be switched with value of 21.5/14.9/9.1/2.9/−3 dB, and the corresponding NF and IP1dB are 3.7/4.9/7.9/12.8/14.3 dB and −23.8/−19.5/−14.8/ −13.1/−8.8 dBm at 33 GHz, respectively. This design is suitable for wideband 5G millimeter-wave communication.

This paper presents compact 24–35 GHz filtering low noise amplifier (LNA) and filtering switch in 28-nm CMOS technology. A compact mixed magnetic-electric coupling circuit is designed, where a transmission zero is introduced out of the passband due to the cancellation of the magnetic and electric couplings. By analyzing the impedance characteristics, this structure can be designed with the impedance conversion function to replace the widely used transformers in integrated circuit designs. It shows the advantages of easy control of coupling coefficient and out-of-band rejection. Then, an LNA employing the magnetic-electric coupling circuits as impedance matching networks is designed. Image rejection can be achieved without increasing the circuit area. Moreover, by loading transistors to this mixed magnetic-electric coupling circuit, the input impedance can be controlled by the parasitic components of the transistor. Subsequently, a filter passband can be switched on and off, realizing a very compact filtering single-pole single-throw (SPST) switch. The fabricated filtering LNA is measured with a 3-dB bandwidth of 24–35 GHz, a noise figure (NF) of 2.4-3.6 dB, a maximum gain of 22 dB, and suppression of better than 25 dBc below 18 GHz. The filtering switch shows a minimum on-state loss of 2.1 dB at 28.6 GHz with better than 12.9 dB rejection below 16 GHz and off-state isolation of higher than 19 dB.

This paper presents a broadband Doherty power amplifier (DPA) using quarter-wavelength ($\lambda $/4) transmission lines with negative characteristic impedance. In conventional DPA designs, the load modulation network is frequency-dependent, leading to bandwidth limitation at the back-off power region. In this design, by integrating two$\lambda $/4 transmission lines with negative characteristic impedance into the main and auxiliary branches, the impedance at the back-off power can be manipulated to maintain high efficiency at back-off power over a wide frequency range. Thus, the operational bandwidth is extended. In circuit realization, the two negative characteristic impedance$\lambda $/4 transmission lines are replaced by paralleled negative LC components. Then, the negative capacitor is combined into the$\pi $-shaped impedance matching network, while the negative inductor is eliminated by introducing Norton transformation. For verification, a broadband DPA with a fractional bandwidth of 108.6% from 0.8 to 2.7 GHz is implemented. The measured saturated output power is 41.8-44 dBm. The saturated and 6-dB back-off power drain efficiencies are 47.6%-84.4% and 39.5%- 52%, respectively. A 20-MHz LTE modulated signal with peak-to- average power ratio (PAPR) of 7.5 dB is also applied to measure the fabricated DPA. After digital predistortion, the adjacent channel leakage ratio (ACLR) better than −45.35 dBc is achieved, and the measured average efficiency is higher than 40% within the operating band.

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50-$\Omega $load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs.

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line,${n}$resonators, and$m$output feeding lines, the$n^{\mathbf {th}}$-order$m$-way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output$Q_{\mathbf {e}}$values. Design theories for obtaining the desired$Q_{\mathbf {e}}$values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to$m$operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure.