VLDB 2026 Research / reviewers in the wild / expert
Sepideh Asadi
dblp:197/9595
· DBLP profile ↗
8ranked-venue papers
4as first author
1since 2021 · last 2022
0000-0001-7505-3172ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 5 · 2 first-authorTheory of computation · 5 · 3 first-author · 1 since 2021Artificial intelligence and machine learning · 2 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | SMT-based verification of program changes through summary repairabstractThis article provides an innovative approach for verification by model checking of programs that undergo continuous changes. To tackle the problem of repeating the entire model checking for each new version of the program, our approach verifies programs incrementally. It reuses computational history of the previous program version, namely function summaries. In particular, the summaries are over-approximations of the bounded program behaviors. Whenever reusing of summaries is not possible straight away, our algorithm repairs the summaries to maximize the chance of reusability of them for subsequent runs. We base our approach on satisfiability modulo theories (SMT) to take full advantage of lightweight modeling approach and at the same time the ability to provide concise function summarization. Our approach leverages pre-computed function summaries in SMT to localize the checks of changed functions. Furthermore, to exploit the trade-off between precision and performance, our approach relies on the use of an SMT solver, not only for underlying reasoning, but also for program modeling and the adjustment of its precision. On the benchmark suite of primarily Linux device drivers versions, we demonstrate that our algorithm achieves an order of magnitude speedup compared to prior approaches. Sepideh Asadi, Martin Blicha, Antti Eero Johannes Hyvärinen, Grigory Fedyukovich, Natasha Sharygina |
Formal Methods Syst. Des. | 1 |
| 2020 | Incremental Verification by SMT-based Summary RepairabstractWe present UPPROVER, a bounded model checker designed to incrementally verify software while it is being gradually developed, refactored, or optimized.In contrast to its predecessor, a SAT-based tool EVOLCHECK, our tool exploits first-order theories available in SMT solvers, offering two more levels of encoding precision: linear arithmetic and uninterpreted functions, thus allowing a trade-off between precision and performance.Algorithmically UPPROVER is based on the reuse and repair of interpolation-based function summaries from one software version to another.UPPROVER leverages treeinterpolation systems in SMT to localize and speed up the checks of new versions.UPPROVER demonstrates an order of magnitude speedup on large-scale programs in comparison to EVOLCHECK and HIFROG, a non-incremental bounded model checker. Sepideh Asadi, Martin Blicha, Antti Eero Johannes Hyvärinen, Grigory Fedyukovich, Natasha Sharygina |
FMCAD | 1 |
| 2020 | Farkas-Based Tree Interpolation
Sepideh Asadi, Martin Blicha, Antti Eero Johannes Hyvärinen, Grigory Fedyukovich, Natasha Sharygina |
SAS | 1 |
| 2018 | Computing Exact Worst-Case Gas Consumption for Smart Contracts
Matteo Marescotti, Martin Blicha, Antti Eero Johannes Hyvärinen, Sepideh Asadi, Natasha Sharygina |
ISoLA (4) | 4 |
| 2018 | Function Summarization Modulo TheoriesabstractSMT-based program verification can achieve high precision using bit-precise models or combinations of different theories. Often such approaches suffer from problems related to scalability due to the complexity of the underlying decision procedures. Precision is traded for performance by increasing the abstraction level of the model. As the level of abstraction increases, missing important details of the program model becomes problematic. In this paper we address this problem with an incremental verification approach that alternates precision of the program modules on demand. The idea is to model a program using the lightest possible (i.e., less expensive) theories that suffice to verify the desired property. To this end, we employ safe over-approximations for the program based on both function summaries and light-weight SMT theories. If during verification it turns out that the precision is too low, our approach lazily strengthens all affected summaries or the theory through an iterative refinement procedure. The resulting summarization framework provides a natural and light-weight approach for carrying information between different theories. An experimental evaluation with a bounded model checker for C on a wide range of benchmarks demonstrates that our approach scales well, often effortlessly solving instances where the state-of-the-art model checker CBMC runs out of time or memory. Sepideh Asadi, Martin Blicha, Grigory Fedyukovich, Antti Eero Johannes Hyvärinen, Karine Even-Mendoza, Natasha Sharygina, Hana Chockler |
LPAR | 1 |
| 2017 | Duality-based interpolation for quantifier-free equalities and uninterpreted functionsabstractInterpolating, i.e., computing safe over-approximations for a system represented by a logical formula, is at the core of symbolic model-checking. One of the central tools in modeling programs is the use of the equality logic and uninterpreted functions (EUF), but certain aspects of its interpolation, such as size and the logical strength, are still relatively little studied. In this paper we present a solid framework for building compact, strength-controlled interpolants, prove its strength and size properties on EUF, implement and combine it with a propositional interpolation system and integrate the implementation into a model checker. We report encouraging results on using the interpolants both in a controlled setting and in the model checker. Based on the experimentation the presented techniques have potentially a big impact on the final interpolant size and the number of counter-example-guided refinements. Leonardo Alt, Antti Eero Johannes Hyvärinen, Sepideh Asadi, Natasha Sharygina |
FMCAD | 3 |
| 2017 | Theory Refinement for Program Verification
Antti Eero Johannes Hyvärinen, Sepideh Asadi, Karine Even-Mendoza, Grigory Fedyukovich, Hana Chockler, Natasha Sharygina |
SAT | 2 |
| 2017 | HiFrog: SMT-based Function Summarization for Software Verification
Leonardo Alt, Sepideh Asadi, Hana Chockler, Karine Even-Mendoza, Grigory Fedyukovich, Antti Eero Johannes Hyvärinen, Natasha Sharygina |
TACAS (2) | 2 |