The immaturity of manufacturing processes often leads to a high incidence of defects in through-silicon vias (TSVs). Prebond TSV testing is essential for optimizing the yield of chip-based integrated circuits. However, current testing methods are limited by their incomprehensive fault coverage and difficulty detecting subtle defects. Furthermore, these methods exhibit significant performance variability due to changes in process angle, power supply voltage, and temperature (PVT). To overcome these limitations, this paper introduces an innovative Ring Oscillator (RO)-based prebond test method specifically designed for TSVs, with a robust system for defect classification and grading. By sampling each node of the RO oscillating ring, the proposed method enhances the resolution of the Time-to-Digital Converter, thereby improving the defect detection capability. Additionally, a weak current source, constructed utilizing the unique properties of MOS transistors, enables the precise detection of open faults, resistive open defects with Ropen ≥ 1.5 K, and leakage defects with Rleak ≤ 10 G. To further mitigate the impact of PVT variations on test results, the paper integrates advanced machine learning techniques for defect classification and grading, providing valuable insights for fault bin classification and fault diagnosis. This innovative approach contributes significantly to the advancement of 3D IC reliability assessment.

Integrated circuits are increasingly sensitive to radiation-induced multi-node upset in advanced CMOS technology. This paper proposes a novel low-power quadruple-node-upset recovery latch (QNU-CPN), which is based on the feedback interconnection of twenty-two input-split C-elements with P-input and N-input (CPNs) to achieve high reliability. Post-layout simulation results for 45nm CMOS by HSPICE technology show that the proposed QNU-CPN latch exhibits a reduction in power consumption by an average of 56.45%, a reduction in power-delay product (PDP) by an average of 56.92%, a reduction in area-power-delay product (APDP) by an average of 58.59%, and a reduction in setup time by an average of 11.11%, in comparison to four other existing quadruple-node upset recovery latch (LDAVPM, QRHIL, QRHIL-LC, MURLAV). Furthermore, this paper proposes the recovery rate calculation algorithm method that can calculate the recovery rate based on the configuration of multiple fault-tolerant components.

Privacy-Preserving Mutual Authentication (PPMA) protocols utilize Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) as security primitives to protect privacy. To ensure the security of Internet of Things (IoT) nodes in untrusted environments, PPMA keys and encrypted data must reside on the same chip. The concept of integrating PUF and TRNG on a single device has thus emerged as a new security paradigm. This paper proposes a novel lightweight, portable, multi-mode reconfigurable integrated PUF-TRNG architecture resistant to machine learning attacks. Through co-design, the architecture achieves the integration and switching among three modes: Arbiter Physical Unclonable Function (APUF), Ring Oscillator Physical Unclonable Function (RO PUF), and TRNG. The APUF mode leverages the RO PUF mode for assistance, endowing it with machine learning resistance, where the highest prediction rates using Logistic Regression (LR), Support Vector Machine (SVM), CMA (Comparative Model Analysis), and Deep Neural Network (DNN) algorithms are only around 60%. Additionally, a lightweight authentication protocol is proposed to further enhance resistance against machine learning attacks. In TRNG mode, the architecture has two outputs, each capable of generating random numbers at 800 Mbps, resulting in a total throughput of 1600 Mbps. The generated random numbers have successfully passed various tests, including NIST SP800-22, NIST SP800-90B, AIS-31, and TESTU01. In the NIST SP800-22 test, the pass rates for both outputs of the Artix-7 and Kintex-7 FPGAs are approximately 99%.

Arbiter physical unclonable function (APUF) is a hardware security primitive that generates security keys by utilizing unavoidable process variations during chip manufacturing. However, the structure based on linear additive function makes it vulnerable to machine learning (ML) attacks. This paper proposes a parallel feedback obfuscation PUF (PFO PUF) design, which uses intermediate arbitration signals of the lower-layer APUF to generate the hidden challenge of the upper-layer APUF, enhancing the overall nonlinearity of the structure. The obfuscation module makes weight judgment for intermediate arbitration signals of upper-layer and lower-layer APUFs, which obfuscates the real response of PUF. We further design a variant of PFO PUF called reconfigured challenge obfuscation PFO PUF (RPFO PUF) and propose its lightweight device authentication protocol. RPFO PUF enhances the resistance of the original PFO PUF against reverse engineering (RE) and improves its Strict Avalanche Criterion (SAC) characteristic by reordering the challenges and incorporating weak PUF responses. The proposed PFO PUF and RPFO PUF were comprehensively evaluated via Python-based simulations and FPGA measurements. In Python simulations, both designs show strong resistance to state-of-the-art ML attacks, with logistic regression (LR), support vector machine (SVM), and covariance matrix adaptation evolution strategies (CMA-ES) yielding near 50% prediction accuracies under various PUF configurations. Although deep neural network (DNN) achieves up to 69.52% prediction accuracy on the PFO PUF, it drops to ∼50% on the RPFO PUF. FPGA results further confirm this, with the (32, 11)-RPFO PUF achieving a maximum prediction accuracy of only 51.47% across all four ML attacks. Moreover, both designs incur low hardware overheads, requiring just 743 and 2145 gate equivalents (GEs), respectively.

Strong Physical Unclonable Functions (PUFs) are critical for lightweight authentication in the Internet of Things (IoT). However, traditional Strong PUF designs are susceptible to advanced Machine Learning (ML) modeling attacks. In this article, we propose a novel modeling-attack-resilient Strong PUF architecture that transforms the challenge-response mapping from a statically approximable function into a mathematically rigorous Keyed Pseudo-Random Function (Keyed-PRF). The proposed architecture features two core innovations: a Sponge-Based Configuration Mechanism (SCM) that utilizes reliable Weak PUFs to dynamically configure the feedback polynomial of a Linear Feedback Shift Register (LFSR), effectively creating a device-specific secret key; and a Response-Modulated State Evolution Mechanism (RM-SEM), where the instantaneous physical responses of the underlying Arbiter PUF determine the evolution step size of the LFSR. This creates a deep temporal feedback loop that transforms the system into a Hidden Markov Model (HMM), blocking gradient-based learning strategies. We also introduce a reliability screening strategy based on a strict bit-error-rate threshold to ensure stability. Experimental results on Xilinx Artix-7 FPGAs demonstrate that the proposed PUF maintains a prediction accuracy of approximately 50% against four mainstream modeling attacks even with 1 million training Challenge-Response Pairs (CRPs). Furthermore, the design exhibits excellent uniformity, uniqueness, and reliability, achieving these security properties with minimal hardware overhead.

True random number generator (TRNG) is a key component in ensuring hardware security, and with the development of technologies such as high-speed communications, there is a higher demand for its generation rate. In this work, an ultra-high throughput rate TRNG based on a scalable cascaded full feedback ring oscillator (CFFRO) as the entropy source circuit is presented and implemented on Xilinx Artix-7, Kintex-7, and zynq UltraScale+ FPGAs devices. Unlike previous works, the proposed CFFRO is designed to be constructed as multiple parallel internal ROs, which, in turn, are sequentially cascaded and coupled to each other to disrupt the frequency spectrum of each ring oscillator and enhance the output uncertainty. Each internal ring oscillator in CFFRO can be used as an output for random numbers, creating multi-channel TRNG with parallel outputs and single-channel TRNG with multi-bit serial outputs. Measurements of the sequences extracted by both random number output schemes of TRNG show good randomness in the NIST SP800-22 suits and high entropy values in both the NIST SP 800-90B and AIS-31 testing suits, and the Dieharder suite verified the robustness under voltage and temperature variations. Moreover, due to the good extensibility of CFFRO, TRNGs with 2–8 channel counts are implemented in this work. At a sampling frequency of 400 MHz, the random sequences generated by 2–8 channel TRNGs can pass the tests.

Physical unclonable functions (PUFs) are critical hardware security primitives that extract entropy from intrinsic manufacturing process variations (MPVs) to generate unique cryptographic responses. They have demonstrated extensive application prospects in lightweight encryption and authentication for Internet of Things (IoT) devices. However, the classic arbiter PUF (APUF) is inherently vulnerable to machine learning (ML) modeling attacks due to the linear mathematical model of its delay circuits. To address this challenge, this article proposes a novel postprocessing obfuscation architecture named recursive Markov chain PUF (RMC PUF). The proposed architecture couples an APUF core with Markov obfuscation modules. By exploiting the intermediate stage responses of the APUF as an entropy source, the system constructs a 1-D recursive stochastic state transition mechanism. This approach recursively transforms and obfuscates the raw entropy based on Markov Chain theory, achieving a PUF system with stability and robust resistance against ML attacks. Through this efficient recursive obfuscation strategy, the design achieves precise utilization of the APUF’s intrinsic entropy. The work is validated through both numerical simulation and FPGA prototyping. Experimental results show that the prototype maintains a high reliability of 98.9%–99.9% within a voltage range of 0.8–1.2 V, and a reliability of 96.1%–99.7% within a temperature range from$- 10~{^{\circ }}$C to$80~{^{\circ }}$C. Comparative analysis indicates that the proposed RMC PUF significantly outperforms existing structures in security, limiting the prediction accuracy of four ML attack models [logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptive evolutionary strategy (CMA-ES)] to no more than 54.72%.

Physical unclonable functions (PUFs) are becoming a crucial solution for addressing hardware security challenges in integrated circuits. However, their widespread adoption is often hindered by the significant overhead of dedicated PUF circuits. This article introduces LBIST-PUF, a novel intrinsic PUF that minimizes overhead by ingeniously reusing the existing logic built-in self-test (LBIST) infrastructure. The design generates unique chip fingerprints through capturing transient responses of the circuit under test (CUT) with a high-frequency configurable clock. To ensure robustness, we incorporate a compensation circuit and a signature correction algorithm, enhancing reliability against environmental variations. Experimental evaluation confirms that the LBIST-PUF achieves near-ideal performance: reliability close to 100%, uniqueness of 50.01%, and a pass rate exceeding 95% on the National Institute of Standards and Technology (NIST) statistical tests. These results underscore the potential of our design as a secure, low-cost authentication solution for Internet of Things (IoT) applications.

Physical Unclonable Functions (PUFs) are crucial for lightweight authentication in the Internet of Things (IoT), but existing PUFs often have poor statistical properties and are vulnerable to machine learning attacks. Designs implementing the Strict Avalanche Criterion (SAC) lack sufficient theoretical foundation. This paper introduces quantitative metrics to evaluate the SAC performance of strong PUFs and conducts rigorous analysis on Arbiter PUFs (APUFs) and their classic variants, addressing imprecision in existing methods. Based on these metrics, we developed an algorithm to optimize the SAC performance of strong PUFs by adjusting the challenge sequences. This optimization improved the SAC performance of the 2-XOR APUF by 59% without additional resource consumption, making it comparable to the 4-XOR APUF; We also provided mathematical proof for the optimal solution. Furthermore, we propose the SAC Optimized Shuffled XOR Arbiter PUF (SOS XOR APUF), which improves SAC performance by 84% compared to the 3-XOR APUF with the same entropy source. It addresses the inherent defect of poor statistical properties when two adjacent bits in the challenge flip, achieving a theoretical response flip probability of 0.5. The SOS XOR APUF resists existing machine learning attacks---including Logistic Regression (LR), Covariance Matrix Adaptation Evolution Strategy (CMA-ES), Artificial Neural Network (ANN), and Deep Neural Network (DNN)---with prediction accuracy below 55%. Finally, we designed and verified an authentication protocol based on this PUF in the ProVerif environment, achieving mutual authentication between IoT devices and servers, preventing secret information from being stolen, and enhancing the security of the PUF structure.

As the CMOS technology continues to shrink, latches are becoming increasingly susceptible to multiple-node-upset caused by charge sharing in radiation environments. In this article, a low-cost quadruple-node-upset (QNU) self-recoverable latch based on cross-interlocking (Quad-CIRC) is proposed. By utilizing four cross-interlocking self-recoverable cells (CIRCs) for interlocking, complete QNU self-recovery is achieved with reduced sensitive nodes. Meanwhile, the majority of currently available QNU self-recoverable latches are primarily composed of C-elements-based redundancy, resulting in a significant increase in area overhead. However, Quad-CIRC effectively reduces area overhead while ensuring hardened capability through cross-interlocking of CIRCs. HSPICE-based simulations in 22 nm CMOS technology demonstrate that Quad-CIRC achieves a reduction of 69.08% on average of power consumption, an increase of 16.83% on average of delay, a reduction of 63.51% on average of power-delay-product (PDP), a reduction of 51.01% on average of area, a reduction of 83.44% on average of area-PDP (APDP), and an increase of 60.49% on average of critical charge, compared to five other QNU self-recoverable latches (QRHIL, MURLAV, LDAVPM,$QR-R_{11}-C_{2}$, and low-delay QNU self-recoverable).

The true random number generator is capable of generating completely random and unpredictable sequences, and plays a crucial role in various fields such as cryptography, encryption communication, and random algorithms. To meet the demand for high-throughput true random number generators in modern high-speed systems, a lightweight TRNG design is proposed. It utilizes a mesh topology of coupled-XOR as entropy source and generates a highly compact and high throughput true random number generator by coupling oscillators in the network. The generated random sequences have successfully passed the NIST SP 800-22, TESTU01, NIST SP 800-90B, and AIS-31 tests. It achieved ultra-high throughput of 2.1Gbps and 2.4Gbps on the Xilinx Artix-7 and Kintex-7 series development boards, respectively, achieving efficient utilization of hardware resources. Compared with other works, this design has significant advantages in terms of resource utilization and throughput.

In IoT devices, True Random Number Generators (TRNGs) play an increasingly important role, and advanced TRNGs must possess high throughput, low resource overhead, and high stability. In this article, we propose a fine-grained entropy extraction circuit based on Self-Timed Ring (STR), which can change the entropy extraction capability by varying the stages of STRs to extract randomness from different entropy sources. Importantly, the throughput of the proposed TRNG can be automatically adjusted according to the frequency of the entropy source, adapting to user requirements. The proposed TRNG is validated on Xilinx Spartan-6, Xilinx Artix-7, and Xilinx Virtex-6 FPGA development boards. It utilizes a three-stage Ring Oscillator (RO) and a five-stage RO for entropy extraction, requiring only 53 LUTs, 32 DFFs, and 62 registers. The generated random numbers of the TRNG, without any post-processing, achieve excellent results in NIST SP 800-22, NIST SP 800-90B, robustness test, universality test, AIS-31, and TEST U01, demonstrating a throughput of 280 Mbps.

Due to the immaturity of the manufacturing process, numerous faults often occur in through-silicon vias (TSVs). Prebond TSV testing is crucial in enhancing the performance and yield of chiplet-based integrated chips. However, most existing test methods suffer from the test resolution and hard-to-detect weak faults. A novel prebond TSV test method based on the pulse is proposed to improve the test circuit. By introducing pMOS as a driver in pulse detection, TSV leakage faults can be directly tested, thus improving the resolution of leakage faults’ detection. In addition, the range of test pulsewidth to digital code conversion is effectively improved by the ring oscillator (RO) for coarse detection and pulse shrinking for fine detection, avoiding the problem of large overheads that would be brought about by solely increasing the pulse shrinking chain. The results validated by HSPICE simulation show that it can detect open faults, resistive open faults with$R_{\text {open}} \gt $$0.9~{\mathrm {K}} {\mathrm {\Omega }}$, leakage faults with$R_{\text {leak}} \lt $$30~{\mathrm {G}} {\mathrm {\Omega }}$, and compound faults consisting of resistive open faults and leakage faults.

Strong physical unclonable functions (PUFs) are promising circuits for lightweight Internet of Things (IoT) authentication and security. However, existing strong PUFs exhibit very low cryptographic nonlinearity (NL), making them vulnerable to machine learning (ML) modeling and cryptanalytic attack. To address this issue, we propose the Bent function PUF (BF PUF) based on Maiorana-McFarland (M-M) constructed Bent functions, which obfuscates the responses of the strong PUF to enhance resistance against modeling attacks. The core idea is to employ the M-M construction method for Bent functions to ensure maximum cryptographic NL to resist modeling attacks. A Feistel network is configured using weak PUF responses as keys to achieve device-specific and unpredictable mappings of input challenges while meeting the requirements of the M-M Bent function construction. A Python-based model of the BF PUF was developed, and simulation results indicate that the cryptographic NL of the proposed BF PUF outperformsk-xorarbiter PUFs (APUFs) (${k} =2$, 4, 6). The proposed BF PUF was also implemented and evaluated on the FPGA hardware platform. The experimental results show that under modeling attacks using four ML algorithms—logistic regression (LR), artificial neural networks (ANNs), deep neural networks (DNNs), and covariance matrix adaptation evolution strategies (CMA-ES)—the best prediction accuracy under these four modeling attack algorithms is 52.60%. The reliability under temperature fluctuations ranging from$- 10~^{\circ }$C to$80~^{\circ }$C is between 84.20% and 99.78%.

As a critical component of 3-D integrated circuits (3D-ICs), the quality of through-silicon vias (TSVs) significantly impacts the yield and reliability of 3D-ICs, especially the clustered faults during manufacturing. In this article, a repair architecture based on TSV misalignment is proposed. This architecture achieves a higher repair rate by physically connecting the signal not to its closest TSV but only to the TSVs far away from each other. Experimental results show that the average repair rate of the proposed architecture increases by 13.42% compared to the existing repair architectures of the same type for clustered faults. Compared to the router-based architecture, the proposed architecture has a similar average repair rate with less than 0.15% difference in fewer than eight clustered faults, reducing the delay and MUX area overhead by 70.27% and 54.17%, respectively.

As a core component in the field of information security, the true random number generator (TRNG) produces high-entropy random numbers by extracting unpredictable noise from the physical environment, exhibiting nonreproducibility and resistance to prediction. To address the challenges posed by interference in high-speed systems, maintaining stable throughput and entropy sources for TRNG, this article proposes an optimized TRNG that utilizes chaotic interference to refresh the cellular automata (IRCA) iterative algorithm. The IRCA-TRNG utilizes a self-timed ring oscillator (STR) and jitter to perturb the operation of chaotic cellular automata (CA) cells, achieving a high-throughput TRNG. The generated random sequences have successfully passed NIST SP800-22, TESTU01, NIST SP800-90B, and AIS-31 tests. A throughput of 1040 Mb/s has been achieved on Xilinx Artix-7 and PYNQ-K2 series development boards. Compared with the state-of-the-art works, the proposed TRNG demonstrates significant advantages in resource utilization and performance quality factors.

The true random number generator (TRNG) is capable of generating completely random and unpredictable sequences. TRNG is an important hardware security primitive, it plays a critical role in identity verification, prevention of replay attacks and key exchange. To meet the demand for high-throughput true random number generators in modern high-speed systems, a lightweight design is proposed. It utilizes a mesh topological of coupled-XOR as entropy source and generates a highly compact and high throughput true random number generator by coupling oscillators in the network. The generated random sequences have successfully passed the NIST SP800-22 and AIS-31 tests. It achieved ultra-high throughput of 2.1Gbps and 2.4Gbps on the Xilinx Artix-7 FPGA and Kintex-7 FPGA, respectively, achieving efficient utilization of hardware resources. Compared with other architectures, this design has significant advantages in terms of throughput and resource utilization.

Arbiter Physically Unclonable Functions (APUFs) are hardware security primitives that leverage manufacturing process variation to generate security keys. They can produce exponential challenge-response pairs (CRPs) with minimal hardware overhead. However, the symmetric nature of linear additive functions makes them vulnerable to modeling attacks rooted in machine learning. To address this issue, this paper introduces a novel design called Parallel Feed Obfuscation PUF (PFO PUF). In this approach, the intermediate decision signals from the lower APUF are used as a concealed challenge for the upper APUF, enhancing the overall nonlinearity of the dual-APUF. Additionally, obfuscation modules are employed to determine the weights of the intermediate decision signals from both the upper and lower APUFs, protecting the actual response. Experimental results demonstrate that the proposed PFO PUF effectively withstands four advanced machine learning attack algorithms, including Logistic Regression (LR), Support Vector Machine (SVM), Deep Feedforward Neural Network (DFNN), and Efficient CANDECOMP/PARAFAC Tensor Regression Network (ECPTRN). The prediction accuracy of these four algorithms is consistently below 66.30%. Compared with other enhanced structures based on APUF, PFO-PUF only uses 493 LUTs and has lower resource overhead.

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

This study presents a pure digital scalable mixed entropy separation structure for the physical unclonable function (PUF) and true random number generator (TRNG), which is implemented on Xilinx field-programmable gate arrays (FPGAs). The mixed entropy separation structure in this study is to solve the problems of unstable output in the existing PUF structure and the poor scalability of the TRNG and PUF design. The proposed design has the following innovations: 1) concept of sensitive entropy and the corresponding processing method are proposed for the first time; 2) design does not need to modify the internal design of the entropy source, and it is suitable for most entropy source arrays; and 3) adjustable PUF bit width and TRNG throughput enhance the scalability of the architecture under different requirements. The structure is simulated and validated on two Xilinx FPGAs and tested under nominal working conditions. The results show that the 512-bit PUF entropy source after treatment is 92.7% more stable than the 1024-bit entropy source before treatment, the random number after treatment passes all types of randomness tests, and the minimum entropy is more than 0.8. Under various conditions within the ranges of 0 °C–80 °C and 0.8–1.2 V, the TRNG output remains stable after treatment; the maximum intra-Hamming distance of the treated PUF is 5.1028%, and the average intra-Hamming distance is 2.7065%.

This paper describes a novel all-digital true rand-om number generator (TRNG) in SRAM-based field programable gate arrays (FPGAs), which utilizes vernier technique to high precisely quantize random edge jitter caused by thermal noise in order for on-die entropy extraction. The TRNG is implemented in three ML605 platforms and experimental result shows that the TRNG presents a high quality of randomness (passing all NIST random tests with high p-values), a high throughput of 127 Mbps, and a good tolerance to bias phenolmenon induced by process, voltage, and temperature (PVT) variations.