While three-dimensional (3D) Memory-on-Logic integration benefits high-performance computing (HPC), it faces critical bottlenecks in power delivery and thermal management. This paper presents a comprehensive power, performance, area, and thermal (PPAT) evaluation of a 3D Memory-on-Logic CPU utilizing Frontside Power Delivery Network (FSPDN) and Backside Power Delivery Network (BSPDN). Our analysis reveals a fundamental trade-off: while BSPDN significantly improves power integrity by reducing logic IR drop by 7.7 × (vs. 3D FSPDN CPU) and 12× (vs. 2D CPU), the extreme substrate thinning required for backside connectivity severely impedes lateral heat dissipation, raising peak temperatures by ~8°C (vs. 3D FSPDN CPU) and ~12°C (vs. 2D CPU). By incorporating thermal-electrical coupling into a spatial-temperature-aware timing analysis, we demonstrate that unlike 3D FSPDN which yields negligible gains over 2D case due to through-silicon via bottlenecks, the superior power integrity of BSPDN decisively outweighs thermal penalties, achieving a net ~30% performance improvement over the 2D counterpart.

In 3D face-to-face (F2F) hybrid bonding ICs, sub-micrometer thin layers lead to an extreme aspect ratio between the lateral dimensions and the vertical thickness. This poses major challenges for finite element method (FEM) thermal simulation. To address this, we introduce ETLA-3D, a thermal FEM methodology based on equivalent thin-layer aggregation, designed specifically for hybrid bonding F2F 3D ICs. The method consolidates the physical properties of thin layers into their neighboring layers by introducing new integral terms into the FEM weak form, greatly reducing the complexity of meshing, the simulation degrees of freedom (DoFs) and the computational cost, while preserving accuracy. Experimental results show that ETLA-3D achieves up to 695.8 × faster runtime compared to the commercial FEM tool (COMSOL Multiphysics), with a maximum absolute error of less than 1.1°C. By combining high accuracy with exceptional efficiency, ETLA-3D establishes a reliable and efficient FEM framework to model the thermal behavior of F2F 3D ICs.

This paper presents a comprehensive power and thermal integrity analysis of a commercial IP based 7nm 3D CPU with a much larger SRAM area compared to its logic section. We systematically investigate the impact of different 3D stacking architectures—Memory-on-Logic (MoL) and Logic-on-Memory (LoM)—combined with both front-side and back-side power delivery networks (FSPDN/BSPDN). A key contribution is a novel lightweight IR drop modeling tool developed in-house, which enables supper fast and highly accurate power integrity estimation at early physical design stages—far before signoff—significantly reducing design iteration time caused by IR violations. This tool also fills a critical gap in commercial EDA support for advanced 3D integration and BSPDN evaluation. Using this tool alongside multi-physics thermal simulations, we compare four 3D design scenarios. Results show that the MoL architecture with BSPDN achieves an optimal balance between power and thermal integrity: it reduces worst-case IR drop in the logic die to just one-fourth of the 2D reference, and lowers peak temperature by over 15°C compared to a LoM counterpart. Further improvements, 50% in IR drop decrease and 14°C temperature reduction, are attainable through TSV optimization and high-thermal-conductivity material integration. This study provides essential 3D architeture, design and technology cooptimization methodologies for future high-perfermance 3D CPUs of advanced technology nodes.

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on the tradeoff between performance, stability, and power efficiency. In addition to size optimization, physical model parameters including CNT density, CNT diameter, and CNFET flat band voltage are evaluated and optimized for CNFET SRAM performance improvement. Optimized CNFET SRAM is compared with state-of-the-art 7-nm FinFET SRAM cell based on Arizona State University [ASAP 7-nm FinFET predictive technology models (PTM)] library. We find that the read, write EDPs, and static power of the proposed CNFET SRAM cell are improved by 67.6%, 71.5%, and 43.6%, respectively, compared with the FinFET SRAM cell, with slightly better stability. CNT interconnects both inside and in-between CNFET SRAM cells are considered to compose an all-carbon-based SRAM (ACS) array which will be discussed in the Part II of this article. A 7-nm FinFET SRAM cell with copper interconnects is implemented and used for comparison.

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of$0.28\times $,$0.52\times $, and$0.76\times $respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.

Differential flip-flop designs for high-speed operations are evaluated for single-event (SE) effects using circuit-level simulations. Results show input dependent SE performance of some differential flip-flop designs. Radiation hardenings by layout optimization for all differential flip-flops and by circuit design for SSTC are discussed.