The introduction of System Level Test (SLT) about a decade ago aimed to a better sustainability for the achievement of the quality objectives required by high performances GPUs and CPUs. The paper intends giving some quantitative information to support this simplified statement. To do this we will report the results of a study conducted by the industrial application of SLT on a product targeted to a high-quality market segment, such as automotive. The discussion will describe the different SLT solutions developed for this new field of application and how it was possible to isolate SLT-only fails and relative functional root causes and cross-correlate traditional ATE test versus SLT screening capability through manufacturing operations.

Automotive systems must reach a high reliability in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible defects that could manifest during lifetime. Burn-In (BI) is a manufacturing test phase used for screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing process of complex Systems on Chip (SoCs) mimicking the operational conditions. This paper aims at describing the motivations for and the effectiveness stemming from combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. Moreover, the paper analyses the required tester architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics is used to demonstrate the possible cost reduction.

In this IP session, there will be 2 presentations focusing on how to increase the in-field quality level of A/MS devices. The 1stpresentation will discuss how to increase the observed return rates of Automotive ICs to 10ppb but at the same time as removing the costly burn in stage.

Environmental and electrical stress phases are commonly applied to automotive devices during manufacturing test. The combination of thermal and electrical stress is used to give rise to early life latent failures that can be naturally found in a population of devices by accelerating aging processes through Burn-In test phases. This paper provides a methodology to evaluate and compare the stress procedures to be run during Burn-In; the proposed method takes into account several factors such as circuit activity, chip surface temperature and current consumption required by the stress procedure, and also considers Burn-In flow and tester limitations. A specific metric called Stress Coverage is suggested summing up all the stress contributions. Experimental results are gathered on an automotive device, showing the comparison between scan-based and functional stress run by a massively parallelized test equipment; reported figures and tables quantify the differences between the two approaches in terms of stress.

New threats, grouped under the name of hardware attacks, became a serious concern in recent years. In a global market, untrusted parties in the supply chain may jeopardize the production of integrated circuits with intellectual-property piracy, illegal overproduction and hardware Trojan-horses (HT) injection. While one way to protect from overproduction is to encrypt the design by inserting logic gates that prevents the circuit from generating the correct outputs unless the right key is used, reducing the number of poorly-controllable signals is known to minimize the chances for an attacker to successfully hide the trigger for some malicious payload. Several approaches successfully tackled independently these two issues. This paper proposes a novel technique based on a multi-objective evolutionary algorithm able to increase hardware security by explicitly targeting both the minimization of rare signals and the maximization of the efficacy of logic encryption. Experimental results demonstrate the proposed method is effective in creating a secure encryption schema for all the circuits under test and in reducing the number rare signals on six circuits over nine, outperforming the current state of the art.

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same time, to preserve test efficiency, diagnosis and debugging abilities. We propose to use the secret-key management policy embedded in the device under test in order to encrypt both control and observed data at test time. This solution does not require additional key management, provides same test/diagnostic and debug facilities as under classical scan design with marginal impacts on area and test time.

In-field test of electronic devices is becoming increasingly important due to the wide adoption of electronic systems in safety-critical applications. Hence, it is crucial to devise and deploy effective solutions supporting the test during the operational phase of all the components of an electronic system, including the memory modules embedded in a SoC. Some key aspects include the possible reuse of HW infrastructures introduced for end-of-manufacturing test, the need for limited intrusiveness with respect to the application, and the achievable defect coverage. The paper discusses the main challenges in this area and possible solutions, as well as future trends.