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Arun Karunanithi

dblp:199/7026 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 32% High-performance computing · 16% Processor architecture and microarchitecture · 16%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
3d-stacked memory		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
GPUs and heterogeneous computing › heterogeneous architecture
accelerated processing unit		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Hardware accelerators and domain-specific architectures › accelerator integration
CPU-GPU integration		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
High-performance computing › supercomputing
exascale computing		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Processor architecture and microarchitecture › multicore design
heterogeneous processor architecture		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Memory systems › DRAM › DRAM architecture
high bandwidth memory		 0.312017
Design and Analysis of an APU for Exascale Computing · HPCA 2017
Integrated circuit design › heterogeneous integration
chiplet-based design		 0.112017
Design and Analysis of an APU for Exascale Computing · HPCA 2017

Methods — techniques the papers use, named apart from their topics

architectural simulation · 0.3
YearPublicationVenuePosition
2017 Design and Analysis of an APU for Exascale Computing
abstract
The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability, and cost. This paper presents a vision for an architecture that can be used to construct exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is the computational building block for an exascale supercomputer. The ENA consists of an Exascale Heterogeneous Processor (EHP) coupled with an advanced memory system. The EHP provides a high-performance accelerated processing unit (CPU+GPU), in-package high-bandwidth 3D memory, and aggressive use of die-stacking and chiplet technologies to meet the requirements for exascale computing in a balanced manner. We present initial experimental analysis to demonstrate the promise of our approach, and we discuss remaining open research challenges for the community.
Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang 0004, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven E. Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan
 HPCA10