We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power-aware behavioral RTL model. To the best of our knowledge, this is the first attempt at addressing the power-aware RTL model generation problem for custom memories. In our method, we identify voltage crossing points in transistors across channel connected components and use these crossing points to transform the RTL for power-awareness closely matching its circuit implementation. Without the proposed abstraction technique to generate power-aware RTL, low-power verification of such memories will need to be done using transistor-level simulations that are prohibitively time-intensive and hence impractical. We check for correctness of these generated power-aware memory models through formal equivalence, symbolic simulations, assertion and simulation based verification. These models are also validated using static power-domain checks. By applying this methodology in a power-aware design and verification framework on a commercial processor, we identified and corrected low power circuit and RTL bugs prior to tape-out.

This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduced and compared to the conventional one in terms of dynamic clock power, leakage, area, timing, and low-voltage operation. Finally, the paper discusses the silicon measurements taken to verify the correct functionality of the new circuit in a 45-nm technology optimized for low standby power.

This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.

In multilevel interconnect structures, the interconnect layers are practically always perpendicular to each other. Due to the capacitive coupling between adjacent layers, the switching activity in one layer produces noise in the others. Often, this interlevel coupling noise is implicitly neglected: only the parallel neighbors of a victim line are considered noisy while the perpendicular conductors located in the layers above and below the victim are assumed to behave as quiet metal planes. However, the error due to this assumption is unclear. It has never been rigorously analyzed or quantified. This paper examines the interlevel coupling noise present at the far end of a victim when a large number of perpendicular aggressors are randomly switching. Each aggressor is modeled as a Markov chain and the victim is modeled as a resistance–inductance–capacitance transmission line. The result is a novel closed-form expression for the power-spectral density of the random switching noise produced by the perpendicular aggressors. It is used to rigorously show that the quiet metal plane assumption is statistically very good when the number of orthogonal aggressors is large and when they are toggling independently. The validity of the quiet metal plane assumption is also discussed when the orthogonal aggressors form wide buses that can be considered sufficiently correlated to produce deterministic simultaneous switching noise.

Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed. They are compared in terms of efficiency, performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible.